Hardware WCK2CK Training Engine Using Meta-EDC Sweeping
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Solution Overview
Problem
Current graphics dual data rate (GDDR5) memory interface buses face challenges in fast clock training, particularly in x16 mode, which can lead to lengthy training times that impede real-time performance requirements, such as screen refresh, due to the need for multiple sweeps to find a phase relationship acceptable to both DRAM components.
Innovation Solution
A method is introduced that determines a timing midpoint between timing values associated with multiple memory components using a meta-error detection code (meta-EDC) value, allowing for faster clock training by performing a single sweep and calculating a meta-EDC midpoint, thereby reducing training time and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple sweeps are performed to find a phase relationship acceptable to both DRAM components, then clock training accuracy is improved, but training time increases significantly
Solution Approach 1:
The patent combines the phase detection results from multiple DRAM components into a single meta-EDC value that represents the aggregate timing midpoint. Instead of performing separate sweeps for each component and then averaging results, the system merges EDC feedback from multiple components during a single sweep to determine a common timing midpoint that satisfies all components simultaneously.
Solution Approach 2:
The patent segments the phase detection process by having each DRAM component independently provide EDC feedback about its timing status (early, late, or transient). These segmented feedback signals are then aggregated through logical operations to determine the overall timing midpoint, allowing parallel processing of multiple component timing requirements.
2Productivity
If a single sweep is used to reduce training time, then training speed is improved, but clock phase alignment accuracy may deteriorate
Solution Approach 1:
The patent employs EDC (Error Detection Code) feedback from each DRAM component during the sweep process. Each component provides feedback indicating whether its write clock is early, late, or transient relative to the reference clock. This feedback mechanism allows the system to accurately determine timing midpoints even within a single sweep, maintaining precision while improving speed.
Solution Approach 2:
The patent uses EDC bits that provide more granular timing information than a simple early/late indication. By utilizing the full range of EDC feedback states (early, transient, late) from multiple components, the system achieves accurate phase alignment with a single sweep rather than requiring multiple coarse-grained sweeps.
3Reliability
If two separate sweeps are performed for each DRAM component, then individual component timing requirements are satisfied, but device complexity and training overhead increase
Solution Approach 1:
The patent creates a universal training procedure that simultaneously satisfies the timing requirements of multiple DRAM components with a single sweep. The meta-EDC mechanism serves multiple functions: it collects feedback from all components, aggregates their timing requirements, and determines a common timing midpoint that works for all components, eliminating the need for separate component-specific sweeps.
Solution Approach 2:
The patent performs preliminary aggregation of EDC feedback from multiple DRAM components during the single sweep process. By collecting and combining timing information from all components in advance, the system can determine the final timing midpoint in one pass rather than requiring sequential sweeps for each component followed by a synthesis step.
Data Source
AI summary
One embodiment of the present invention sets forth a technique for performing high-performance clock training. One clock training sweep operation is performed to determine phase relationships for two write clocks with respect to a command clock. The phase relationships are generated to satisfy timing requirements for two different client devices, such as GDDR5 DRAM components. A second clock training sweep operation is performed to better align local clocks operating on the client devices. A voting tally is maintained during the second clock training sweep to record phase agreement at each step in the clock training sweep. The voting tally then determines whether one of the local clocks should be inverted to better align the two local clocks.