WCSP Edge Pad Layout for Visible Solder Fillets

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Wafer-level packaged semiconductor chips (WCSPs) currently cannot form visible solder fillets beyond their outer perimeter, preventing them from being used in electronic devices that require post-assembly visual solder inspections for quality verification, despite offering manufacturing efficiencies.

Innovation Solution

The WCSP design includes conductive members positioned close to the side surfaces, allowing solder fillets to extend beyond the package perimeter for visual inspection, while maintaining manufacturing efficiency through wafer-level packaging techniques.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If wafer-level packaging techniques are used to form WCSPs, then manufacturing efficiency is improved, but the ability to form visible solder fillets for visual inspection is lost

Engineering Contradiction:
Improvemanufacturing efficiencyVSAvoidvisual inspection capability
Core Design Contradiction:
ProductivityVSDifficulty of detecting and measuring

Solution Approach 1:

The conductive members are positioned at the edge of the WCSP package, transitioning from a conventional centralized arrangement to an edge-positioned configuration. This spatial repositioning allows solder fillets to extend beyond the package perimeter in a lateral dimension, enabling visual inspection while preserving the wafer-level packaging manufacturing efficiency.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The insulating member is configured to extend only partially over the device side, specifically not extending between the conductive member and the outer perimeter. This localized modification creates an exposed region at the edge that facilitates solder fillet visibility, while the rest of the package maintains its standard insulating structure for manufacturing efficiency.

Inventive Principle:
Principle #3Local quality

2Difficulty of detecting and measuring

If conductive members are positioned close to the outer perimeter to enable visible solder fillets, then visual inspection capability is improved, but the insulating member configuration becomes more complex

Engineering Contradiction:
Improvevisual inspection capabilityVSAvoidinsulating member configuration
Core Design Contradiction:
Difficulty of detecting and measuringVSDevice complexity

Solution Approach 1:

The insulating member is intentionally omitted from the region between the conductive member and the outer perimeter of the WCSP. This extraction of the insulating material from a specific location creates the necessary exposed area for solder fillet visibility, while minimizing the overall complexity by only modifying the insulating member configuration in the essential region.

Inventive Principle:
Principle #2Taking out (Extraction)

3Difficulty of detecting and measuring

If the insulating member does not extend between the conductive member and the outer perimeter, then solder fillet visibility is improved, but the protective coverage of the device side is reduced

Engineering Contradiction:
Improvesolder fillet visibilityVSAvoidprotective coverage
Core Design Contradiction:
Difficulty of detecting and measuringVSReliability

Solution Approach 1:

The insulating member provides protective coverage over most of the device side while deliberately leaving the edge region between the conductive member and outer perimeter exposed. This localized differentiation allows the package to maintain reliability through extensive insulating coverage while enabling solder fillet visibility in the specific region where exposure is needed.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11855024B2Wafer chip scale packages with visible solder fillets
Publication Date: 2023.12.26 TEXAS INSTRUMENTS INC
  • US11855024B2 patent drawing
  • US11855024B2 patent drawing
  • US11855024B2 patent drawing

AI summary

In some examples a wafer chip scale package (WCSP) includes a semiconductor die having a device side in which a circuit is formed, and a redistribution layer (RDL) coupled to the device side that is positioned within an insulating member. In addition, the WCSP includes a scribe seal circumscribing the circuit along the device side, wherein the RDL abuts the scribe seal. Further, the WCSP includes a conductive member coupled to the RDL. The conductive member is configured to receive a solder member, and the insulating member does not extend along the device side of the semiconductor die between the conductive member and a portion of an outer perimeter of the WCSP closest to the conductive member.