Watchdog Timer Failure Diagnosis in Electronic Control Devices
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Solution Overview
Problem
Existing systems face challenges in performing failure diagnosis of a watchdog timer (WDT) without causing delays in the startup of a CPU, especially in systems with high frequency of startup and sleep modes, which can adversely affect system reliability.
Innovation Solution
An electronic control device is designed with a processing unit that transitions to a sleep mode and includes a watchdog timer with a time counter resetting via pulse signals, a latch circuit to output signals indicating overflow, and an AND circuit to calculate logical products of output enable signals, allowing for failure diagnosis after pulse signal cessation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the CPU carries out failure diagnosis for the WDT at the time of startup, then the WDT failure can be detected, but the CPU startup time is prolonged which adversely affects system reliability
Solution Approach 1:
The failure diagnosis function is executed in advance during the transition to sleep mode before the CPU enters startup. The diagnosis result is stored in advance, so when the CPU starts up, the diagnostic information is already available without delaying the startup process. This preliminary execution of the diagnostic function during sleep mode transition resolves the contradiction by separating the timing of diagnosis execution from CPU startup.
Solution Approach 2:
The system dynamically adjusts when the failure diagnosis is performed based on the operational state. Instead of fixed startup-time diagnosis, the system performs diagnosis during sleep mode transitions and makes the diagnostic results available during startup. This dynamic timing adjustment allows the system to maintain reliability monitoring while optimizing startup performance.
2Speed
If the CPU frequently transitions between startup and sleep modes, then the system can respond quickly to changes, but performing WDT diagnosis at each startup reduces overall system reliability
Solution Approach 1:
The failure diagnosis is performed in advance during the transition to sleep mode, before the CPU enters startup. This preliminary execution ensures that diagnostic results are ready when startup occurs, allowing frequent transitions without compromising reliability checks. The diagnosis is prepared beforehand, so rapid CPU transitions do not sacrifice diagnostic thoroughness.
Solution Approach 2:
The failure diagnosis is performed periodically during sleep mode transitions rather than at every startup. This periodic execution during less critical phases (sleep transitions) allows the system to maintain reliability monitoring while enabling rapid CPU startup and sleep transitions. The periodic nature of diagnosis during sleep transitions prevents reliability degradation despite frequent CPU state changes.
Data Source
AI summary
The present invention provides an electronic control device including: a processing unit having a function of transition to a sleep mode; and a watch dog timer having a time counter that resets in response to a pulse signal outputted from the processing unit at certain intervals, this watch dog timer outputting a signal having a level inverted according to the existence or absence of overflow occurrence, in which the electronic control device further includes a latch circuit that latches the signal outputted from the watch dog timer and outputs a signal obtained through the latching as a first output enable signal, and the processing unit stops outputting the pulse signal before transition to the sleep mode, and carries out failure diagnosis of the watch dog timer based on the first output enable signal outputted from the latch circuit after output of the pulse signal is stopped.