Weak Cell Management in Memory Devices
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Solution Overview
Problem
Memory devices face data retention issues due to leakage currents in MOS transistors, leading to weak cells with shorter data retention times, which can result in data loss and reduced yield, necessitating frequent refresh operations and accurate testing to ensure reliability.
Innovation Solution
A memory device equipped with a weak cell information storage unit, an error correction code (ECC) circuit, and a refresh control unit that detects and corrects errors in weak cells using parity information, allowing for extended refresh cycles and replacement of weak cells with redundancy cells to maintain data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells with short data retention time (weak cells) are processed as fails during testing, then data reliability is maintained, but manufacturing yield decreases
Solution Approach 1:
The patent performs preliminary identification of weak cells during manufacturing testing by detecting data retention time. Addresses are stored in a lookup table (LUT) for these identified weak cells before the product reaches the customer. This preliminary action allows the system to prepare correction mechanisms in advance, enabling weak cells to be used rather than discarded, thus improving yield while maintaining reliability.
Solution Approach 2:
The patent implements beforehand cushioning by storing parity information and addresses of weak cells in the LUT during manufacturing. This preparatory cushioning mechanism ensures that when weak cells are encountered during operation, the system already has the necessary correction data ready, preventing data errors before they occur and allowing weak cells to be salvaged.
2Reliability
If refresh operations are performed frequently to maintain data in weak cells, then data retention is improved, but power consumption increases
Solution Approach 1:
The patent applies local quality by treating weak cells differently from normal cells. Instead of refreshing all cells uniformly, the system specifically targets only weak cells identified in the LUT for refresh operations and error correction. This localized approach maintains data retention for problematic cells while avoiding unnecessary refresh operations on normal cells, thereby reducing overall power consumption.
Solution Approach 2:
The system implements self-service by automatically detecting and correcting errors in weak cells using stored parity information from the LUT, without requiring external intervention or frequent comprehensive refresh cycles. The ECC circuit autonomously manages weak cell corrections, reducing the burden on the refresh mechanism and lowering power consumption.
3Reliability
If ECC correction is applied to weak cells, then data error rate decreases, but device complexity increases
Solution Approach 1:
The patent uses preliminary action by pre-storing parity information and weak cell addresses in the LUT during manufacturing. This pre-computation eliminates the need for complex real-time parity generation circuits during operation. The ECC correction process becomes simpler because the reference data is already prepared, reducing the complexity burden of error correction functionality.
Solution Approach 2:
The system employs copying by storing copies of parity information and weak cell addresses in the LUT during manufacturing testing. These copied data structures serve as reference for rapid error correction without requiring complex real-time computation. The copying approach simplifies the operational complexity by replacing complex algorithms with straightforward table lookups and comparisons.
Data Source
AI summary
A memory device may include: a plurality of memory cells; a weak cell information storage unit suitable for storing a weak address and parity information corresponding to one or more weak cells having a shorter data retention time than a reference time, among the plurality of memory cells; an ECC (Error Correction Code) circuit suitable for detecting and correcting an error bit of the one or more weak cells using the parity information; and a refresh control unit suitable for controlling the plurality of memory cells to be refreshed at a cycle equal to or more than the reference time.