Weak Erase Operation for Charge-Trapping Memory Data Retention
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Solution Overview
Problem
Charge loss in charge-trapping memory devices leads to a decrease in threshold voltage (Vth) over time, causing data retention issues and reduced reliability, as charges are trapped in the nitride layer of the tunneling layer, resulting in a widened Vth distribution and impaired ability to accurately read data states.
Innovation Solution
A data retention operation is performed after programming, involving weak erase voltages applied to memory cells to reduce charge storage in the nitride of the tunneling layer, with optimized voltages based on testing to maintain data integrity, including a negative gate-to-channel voltage for memory cells, which is weaker than regular erase operations, to minimize long-term data retention losses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If charges are trapped in the nitride layer of the tunneling layer during programming, then data storage is achieved, but charge loss occurs over time leading to widened Vth distribution and reduced data retention
Solution Approach 1:
A weak erase operation is performed immediately after programming to preemptively address charge loss before it significantly degrades data retention. This preliminary action removes charges from the nitride layer that would otherwise cause Vth widening over time, thereby maintaining narrow Vth distribution and improving data retention without requiring strong erase operations that could disrupt stored data.
2Reliability
If a strong erase operation is performed to remove charges from the nitride layer, then charge loss is reduced, but data integrity may be compromised and Vth distribution may widen
Solution Approach 1:
The erase operation parameters are changed by applying a weak erase voltage (first voltage level) that is insufficient to completely remove charges from the nitride layer but sufficient to reduce charge loss. This parameter change allows charge removal without causing significant Vth widening or compromising data integrity, as the weak voltage does not induce strong tunneling currents that would disrupt stored data states.
3Reliability
If no erase operation is performed after programming, then data storage is maintained, but charge loss in the nitride layer causes Vth to decrease over time and data retention deteriorates
Solution Approach 1:
A weak erase operation is performed immediately after programming to preemptively address charge loss before it significantly degrades data retention. This preliminary action removes charges from the nitride layer that would otherwise cause Vth widening over time, thereby maintaining narrow Vth distribution and improving data retention without requiring strong erase operations that could disrupt stored data.
4Reliability
If weak erase voltages are applied to reduce charge storage in the nitride layer, then data retention is improved, but the erase effect is limited and may not fully remove charges
Solution Approach 1:
The weak erase operation is performed continuously or repeatedly after programming to maintain charge removal effectiveness over time. By applying the weak erase voltage multiple times or in continuous manner, the operation progressively removes charges from the nitride layer without causing Vth widening, achieving both data retention improvement and sufficient charge removal to prevent long-term degradation.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces charge loss in the nitride layer, maintaining a narrow Vth window and improving data retention characteristics, ensuring accurate data readback and enhanced reliability of memory cells over time.
Implementation Method 1
A charge-trapping material can be used in memory devices to store a charge which represents a data state. The charge-trapping material can be arranged vertically in a three-dimensional (3D) stacked memory structure, or horizontally in a two-dimensional (2D) memory structure.
Implementation Method 2
A first data retention operation can be performed concurrently for all memory cells of a block so that the additional time used is a small fraction of the overall programming time. The data retention operation involves applying weak erase voltages to the memory cells.
Data Source
AI summary
Techniques are provided to improve long term data retention in a charge-trapping memory device. In addition to a primary charge-trapping layer in which most charges are stored, the memory device may include a tunneling layer comprising an engineered tunneling barrier such as oxide-nitride-oxide. The nitride in the tunneling layer may also store some charges after programming. After the programming, a data retention operation is performed which de-traps some electrons from the tunneling layer, in addition to injecting holes into the tunneling layer which form neutral electron-hole dipoles in place of electrons. These mechanisms tend to lower threshold voltage. Additionally, the data retention operation redistributes the electrons and the holes inside the charge-trapping layer, resulting in an increase in threshold voltage which roughly cancels out the decrease when the data retention operation is optimized.


