Screening Weak Memory Cells Using Adjustable Leakage Stress
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Solution Overview
Problem
Current methods for screening weak memory cells in semiconductor devices are inadequate as they often damage the devices, require high voltage or temperature, and are not flexible enough to differentiate between strong and weak cells effectively.
Innovation Solution
A scheme that uses a leakage stress delivery circuitry (LSDC) coupled with an induced leakage adjustment control (ILAC), comprising PMOS and NMOS transistors controlled by stress-inducing signals, to apply adjustable leakage stress to data lines, allowing a sense amplifier to detect and track pass/fail thresholds without damaging the cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If voltage and temperature controls are used to screen weak cells, then weak cells can be differentiated from strong cells, but the devices may be damaged due to excessive stress
Solution Approach 1:
The patent applies controlled parameter changes by introducing adjustable leakage stress through the ILAC circuit that can modify the effective threshold voltage of transistors. This allows gradual adjustment of stress levels to differentiate weak cells without applying excessive voltage or temperature that would cause damage. The leakage stress parameter is tuned to achieve optimal differentiation while preserving device integrity.
Solution Approach 2:
The patent introduces an intermediary leakage stress delivery circuitry (LSDC) with PMOS and NMOS transistors that mediates between the test system and the memory cells. This intermediary circuit applies controlled leakage current to simulate threshold voltage variations, enabling weak cell detection without directly applying harmful high voltage or temperature stress to the cells themselves.
2Measurement precision
If back-body bias is applied to control transistor driving strength, then weak cells can be identified, but it is difficult to determine the appropriate bias level without damaging devices
Solution Approach 1:
The patent implements dynamic control of leakage stress through the ILAC circuit, which can adjust the stress level adaptively during testing. The system dynamically tunes the leakage current to achieve optimal differentiation between weak and strong cells, eliminating the need for predetermined static bias levels. This dynamic adjustment simplifies operation by automatically finding the appropriate stress level.
Solution Approach 2:
The patent incorporates feedback mechanisms where the sense amplifier monitors cell responses to leakage stress and this information feeds back to the ILAC circuit. The feedback loop allows the system to automatically adjust the leakage stress level based on observed cell behavior, making the testing process easier to operate without requiring manual determination of optimal bias levels.
3Productivity
If device size is shrunk to increase density, then more cells fit in the device, but transistor threshold voltage variation increases making weak cell identification more difficult
Solution Approach 1:
The patent compensates for threshold voltage variations in shrunk devices by introducing adjustable leakage stress that can be tuned to match the increased variation range. The ILAC circuit modifies effective threshold voltages through controlled leakage current, allowing differentiation of weak cells even when natural threshold variations are larger due to scaling. This parameter adjustment restores measurement precision despite size reduction.
4Reliability
If extensive testing is performed to ensure device operability, then reliability increases, but testing time and complexity increase
Solution Approach 1:
The patent performs preliminary weak cell identification using the leakage stress method before final device operation or burn-in testing. By screening out weak cells early using the adjustable leakage stress approach, the need for extended burn-in periods is reduced. This preliminary action maintains reliability assurance while significantly reducing overall testing time.
Data Source
AI summary
A novel scheme for screening weak memory cell includes a cell coupled to a leakage stress delivery circuitry (LSDC), which, in turn, is coupled to an induced leakage adjustment control (ILAC). The LSDC includes a combination of PMOS transistors, NMOS transistors or both PMOS and NMOS transistors that are controlled by a plurality of stress inducing signals. The PMOS and/or NMOS transistors of the LSDC are coupled to a pair of complementary data lines. The complementary data lines are inputs to a sense amplifier and are outputs of a write driver. The ILAC controls the quantity of the leakage stress applied through the LSDC to the pair of complementary data lines. The ILAC further includes a leakage varying circuitry that is configured to adjust the leakage stress applied to the complementary data lines through the LSDC. The applied leakage stress is adjusted to establish a desired pass/fail threshold and to detect other process variations or defects so that the sense amplifier can be applied to detect the voltage differential during a read operation. The applied leakage stress can also be applied to write driver circuitry such that a write driver along with the applied stress provide enough voltage level to screen difficult-to-write cell from a easy-to-write cell during a write operation. The plurality of stress inducing signals are controlled such that the appropriate leakage stress may be applied to force a leakage to Vdd or Vss associated with the cell through the complementary data lines.