Weakly-Ordered Memory Barrier Optimization via LPAR Store Queue
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Solution Overview
Problem
In weakly-ordered memory systems, existing barrier implementations often cause performance delays by ordering unnecessary stores, as they enforce cross-thread ordering regardless of whether the thread has read from updated storage locations, leading to inefficiencies in ensuring causality and atomicity.
Innovation Solution
The proposed solution involves optimizing the store queue by using logical partition (LPAR) information and L1 cache hit/miss conditions to precisely apply the ordering effects of barriers, thereby ignoring unnecessary dependency chains and reducing undue ordering effects, especially for stores that do not hit in the L1 cache or are on different LPARs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If cross-thread ordering is enforced for all stores regardless of L1 cache hit/miss conditions, then causality and atomicity are ensured, but performance delays occur due to unnecessary ordering of stores
Solution Approach 1:
The patent applies different ordering rules to different stores based on their L1 cache hit/miss status. Stores that hit in L1 cache are ordered across threads to ensure causality, while stores that miss in L1 cache are not ordered, avoiding unnecessary performance delays. This local differentiation resolves the contradiction by making the ordering behavior adaptive to the specific characteristics of each store operation.
Solution Approach 2:
The patent changes the ordering parameter based on the L1 cache hit/miss condition. When a store hits in L1 cache, full ordering is applied to ensure causality and atomicity. When a store misses in L1 cache, ordering is relaxed to improve performance. This dynamic parameter adjustment resolves the contradiction between reliability and productivity.
2Reliability
If barrier instructions order all subsequent stores, then atomicity is maintained, but efficiency is reduced by propagating stores that do not require atomicity across threads
Solution Approach 1:
The patent applies atomicity guarantees selectively based on L1 cache hit/miss conditions. Stores that hit in L1 cache maintain full atomicity ordering through barriers, while stores that miss in L1 cache are excluded from this ordering. This local quality approach ensures atomicity where needed while improving efficiency by avoiding unnecessary ordering of stores that don't require it.
Solution Approach 2:
Instead of applying full ordering to all stores after a barrier, the patent applies partial ordering only to stores that hit in L1 cache. This partial action approach maintains the necessary atomicity guarantees while avoiding the excessive ordering of stores that miss in L1 cache, thereby resolving the contradiction between reliability and productivity.
3Reliability
If dependency chains are established for all stores in the store queue, then synchronization is ensured, but complexity increases due to tracking unnecessary dependencies
Solution Approach 1:
The patent establishes dependency chains selectively based on L1 cache hit/miss status. Dependency tracking is applied only to stores that hit in L1 cache, while stores that miss in L1 cache are excluded from dependency tracking. This local quality approach ensures synchronization for critical stores while reducing the complexity of tracking unnecessary dependencies across all stores.
Solution Approach 2:
The patent extracts unnecessary dependency chains from the store queue by identifying and excluding stores that miss in L1 cache from dependency tracking. This extraction reduces the complexity of the dependency graph while maintaining synchronization guarantees for stores that actually require it, resolving the contradiction between reliability and device complexity.
Data Source
AI summary
A technique for operating a lower level cache memory of a data processing system includes receiving an operation that is associated with a first thread. Logical partition (LPAR) information for the operation is used to limit dependencies in a dependency data structure of a store queue of the lower level cache memory that are set and to remove dependencies that are otherwise unnecessary.