Wear Leveling Controller for Non-Volatile Memory
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Solution Overview
Problem
Conventional memory systems with non-volatile memory experience reduced lifespan due to concentrated access on specific physical addresses, leading to uneven wear and tear, which is mitigated by wear leveling processes that redistribute access across memory cells.
Innovation Solution
A memory system with a controller that associates logical addresses with physical addresses in a one-to-one manner, using a process of updating the correspondence between addresses to distribute access evenly, including a first updating and a second updating based on distance and origin information to shift the mapping and prevent exhaustion of specific locations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If wear leveling process is executed to redistribute access across memory cells, then the lifespan of non-volatile memory is extended, but the device complexity increases due to address mapping management
Solution Approach 1:
The patent segments the address mapping process into two distinct parts: a first updating process that handles initial address associations, and a second updating process that handles subsequent redistributions. This segmentation allows the system to manage wear leveling complexity in a structured manner, where each segment handles specific aspects of address mapping without requiring complete remapping operations.
Solution Approach 2:
The patent implements preliminary action by establishing initial address mappings through the first updating process before wear leveling becomes necessary. This preliminary setup creates a baseline mapping structure that can be efficiently adjusted later through the second updating process, rather than starting from scratch during wear leveling operations.
2Reliability
If conventional wear leveling is used to prevent concentrated access, then memory cell exhaustion is delayed, but the process requires complex address translation mechanisms
Solution Approach 1:
The address translation mechanism is segmented into two updating processes: the first updating establishes initial logical-to-physical address mappings, while the second updating redistributes accesses for wear leveling. This segmentation simplifies the overall complexity by breaking down the translation mechanism into manageable, specialized sub-processes rather than requiring a single complex translation system.
Solution Approach 2:
The patent changes the parameter of address mapping updates by introducing a two-stage updating approach. The first updating sets initial parameters (address associations), and the second updating modifies these parameters (redistributes mappings) based on wear leveling needs. This parameter change strategy allows flexible adaptation without requiring complete reconfiguration of the address translation mechanism.
Data Source
AI summary
According to one embodiment, a memory system includes a non-volatile first memory, and a controller. The controller associates a first number of consecutive logical addresses with the first number of physical addresses which are included in a second number of consecutive physical addresses of the first memory. The controller executes a first updating and a second updating. The first updating includes associating a first physical address among the second number of physical addresses with a first logical address. The second updating includes obtaining a second logical address which is away from the first logical address by a value corresponding to distance information on the basis of origin information and the distance information and associating, with the second logical address, a second physical address which had been associated with the first logical address before the first updating is executed.