Wear Leveling for Ferroelectric Memory via Section Segmentation
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Solution Overview
Problem
Existing memory devices, particularly non-volatile ferroelectric RAM (FeRAM), face limitations in memory cell reliability due to limited program and erase cycling endurance, which affects performance and lifetime.
Innovation Solution
The implementation of a method and electronic memory device that supports wear leveling for random access and ferroelectric memory, allowing for the distribution of program and erase cycles across a larger wear-leveling pool, thereby reducing the physical cycle count on each page and mitigating the risk of premature device failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If data is stored in a limited pool of memory pages, then random access performance is improved, but wear leveling effectiveness deteriorates due to concentrated program and erase cycles on the same pages
Solution Approach 1:
The memory device is divided into multiple sections, each with its own set of latches and sense components. The wear leveling pool is segmented across these sections, allowing program and erase cycles to be distributed across different physical pages while maintaining logical address space continuity. This segmentation enables the system to achieve both fast access (by keeping related data in the same section) and wear leveling (by distributing writes across sections).
Solution Approach 2:
The patent introduces a new dimension to the wear leveling problem by utilizing the section architecture as an additional spatial dimension. Instead of only distributing data across pages within a single section, the system can now distribute data across multiple sections, effectively adding a second spatial dimension to the wear leveling pool. This allows for significantly larger wear leveling pools without increasing access latency, as data can be moved between sections while maintaining fast access through the sectioned architecture.
2Reliability
If a larger wear-leveling pool is used to distribute cycles, then reliability is improved, but access time and complexity increase
Solution Approach 1:
By segmenting the memory into multiple sections with dedicated latches and sense components, the system can maintain a large wear leveling pool without increasing access time. When data needs to be accessed, the relevant section can be quickly activated, and the data can be retrieved from the associated latches without needing to search through the entire memory space. This segmentation allows the system to achieve both large wear leveling pools and fast access times.
Solution Approach 2:
The latches in each section are pre-configured to hold data from the associated memory pages. When a read operation is initiated, the data is already positioned in the latches and can be quickly transferred to the output buffer without requiring extensive data movement or processing. This preliminary positioning of data in the latches significantly reduces access time, even when the wear leveling pool spans multiple sections.
3Reliability
If data is copied between sections through error correction circuit, then error correction capability is improved, but device complexity increases
Solution Approach 1:
The error correction circuit is designed to perform multiple functions: it can correct errors during normal read operations, correct errors during wear leveling copy operations between sections, and verify data integrity during page migration. By making the error correction circuit multi-functional, the system achieves robust error correction capability without adding separate dedicated circuits for each function, thereby limiting the increase in device complexity.
Solution Approach 2:
The latches serve as an intermediary buffer between the memory sections and the error correction circuit. When data needs to be copied between sections, it is first loaded into the latches, then transferred through the error correction circuit for verification and correction, and finally written to the destination section. This intermediary approach allows for systematic error correction without requiring complex direct point-to-point error correction mechanisms between all possible section pairs.
Data Source
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AI summary
Methods, systems, and devices related to wear leveling for random access and ferroelectric memory are described. Non-volatile memory devices, e.g., ferroelectric random access memory (FeRAM) may utilize wear leveling to extend life time of the memory devices by avoiding reliability issues due to a limited cycling capability. A wear-leveling pool, or number of cells used for a wear-leveling application, may be expanded by softening or avoiding restrictions on a source page and a destination page within a same section of memory array. In addition, error correction code may be applied when moving data from the source page to the destination page to avoid duplicating errors present in the source page.