Wear-Leveling Manager for Memory Subsystems

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Solution Overview

Problem

Memory subsystems, particularly those using PCM technology, face uneven wear distribution leading to reduced longevity due to inherent write skews and proximity disturb effects, which existing technologies fail to address effectively.

Innovation Solution

A wear-leveling manager and cartridge manager are implemented to identify and invalidate low-write count chunks, organizing them into 'cartridges' to distribute wear evenly, thereby minimizing partition collisions and extending the operational life of memory components.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Duration of action of stationary object

If data is written to memory components without wear-leveling, then write operations are simple and fast, but wear distribution becomes uneven leading to reduced longevity

Engineering Contradiction:
Improvelongevity of memory componentsVSAvoidcomplexity of wear-leveling management
Core Design Contradiction:
Duration of action of stationary objectVSDevice complexity

Solution Approach 1:

A wear-leveling manager is introduced as an intermediary component between the host system and memory components. This manager maintains a data structure tracking write counts for each memory chunk and intercepts write requests to redirect them to low-write-count chunks, thereby distributing wear evenly without requiring changes to the memory components themselves or the host system

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The system performs self-service wear-leveling by automatically tracking and managing its own wear patterns. The wear-leveling manager monitors write counts and autonomously redirects write requests to balance wear distribution, eliminating the need for external intervention or complex host-system modifications

Inventive Principle:
Principle #25Self-service

2Productivity

If conventional write operations are used, then write speed is maintained, but write amplification increases due to uneven wear distribution

Engineering Contradiction:
Improvewrite operation efficiencyVSAvoidwrite amplification and power consumption
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The wear-leveling manager performs preliminary actions by pre-tracking write counts for all memory chunks and maintaining an organized data structure before write requests arrive. This allows write requests to be immediately redirected to optimal chunks without additional overhead, preventing write amplification rather than correcting it afterward

Inventive Principle:
Principle #10Preliminary action

3Reliability

If existing wear-leveling technologies are applied, then some wear distribution is improved, but proximity disturb effects are not effectively addressed

Engineering Contradiction:
Improvewear distribution uniformityVSAvoidproximity disturb effects
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The wear-leveling manager implements feedback by continuously monitoring write counts for each memory chunk and using this information to make real-time decisions about where to direct write requests. This feedback mechanism ensures that chunks experiencing higher wear are avoided, thereby addressing both wear distribution uniformity and proximity disturb effects

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11455242B2Scrubber driven wear leveling in out of place media translation
Publication Date: 2022.09.27 MICRON TECHNOLOGY INC
  • US11455242B2 patent drawing
  • US11455242B2 patent drawing
  • US11455242B2 patent drawing

AI summary

A process for wear-leveling in a memory subsystem where references to invalidated chunks and a write count for each of the invalidated chunks of a memory subsystem are received by a wear-leveling manager. The wear-leveling manager orders the received references to the invalidated chunks of the memory subsystem in a tracking structure based on the write count of each of the invalidated chunks, and provides a reference to at least one of the invalidated chunks based on the ordering from the tracking structure to a write scheduler to service a write request, wherein the memory subsystem is wear-leveled by biasing the order of the invalidated chunks to prioritize low write count chunks.