Wear-Levelling Module for Memory Lifetime Extension
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Solution Overview
Problem
Non-volatile memory devices face wear out due to repeated program/erase cycles, leading to increased bit errors and reduced lifespan, particularly in flash memories and phase change memories, where high temperatures cause material stress and metal oxide layer degradation.
Innovation Solution
A method of wear-levelling that identifies static memory states and moves them to free memory locations in write-heavy regions within a storage system, balancing writes across all memory blocks to extend the lifespan of memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of stationary object
If wear-levelling is performed by moving static memory states to free memory locations in write-heavy regions, then the lifetime of memory devices is extended, but the device complexity increases due to additional identification and data movement operations
Solution Approach 1:
The system performs preliminary identification of static memory states and free memory locations before executing the data movement operation. By pre-identifying candidate locations and assessing their suitability for wear-levelling, the system prepares the necessary information in advance, reducing the complexity of the actual execution phase while achieving extended memory lifetime through balanced write distribution
Solution Approach 2:
The patent introduces a wear-levelling module as an intermediary component that mediates between the memory controller and the memory array. This intermediary layer handles the complex tasks of identifying static memory states, selecting appropriate free memory locations in write-heavy regions, and coordinating data movement, thereby isolating the complexity from the core memory operations and enabling lifetime extension without proportionally increasing overall system complexity
2Reliability
If static memory states are moved to free memory locations in write-heavy regions, then writes are balanced across all memory blocks, but the productivity decreases due to additional data movement operations
Solution Approach 1:
The wear-levelling operation is applied selectively rather than uniformly across all memory blocks. The system identifies specific free memory locations in write-heavy regions and moves static memory states only to those targeted locations. This localized approach ensures write balancing where it is most needed while minimizing unnecessary data movement operations, thereby maintaining productivity while achieving improved write distribution balance
Solution Approach 2:
The system performs wear-levelling partially by selecting only certain static memory states and certain free memory locations for the data movement operation, rather than moving all static data to all available locations. This partial action approach achieves sufficient write balancing to improve reliability without the excessive productivity loss that would result from comprehensive wear-levelling of all memory blocks
Data Source
AI summary
Broadly speaking, embodiments of the present technique provide apparatus and methods for improved wear-levelling in (volatile and non-volatile) memories. In particular, the present wear-levelling techniques comprise moving static memory states within a memory, in order to substantially balance writes across all locations within the memory.