Wear Leveling in Non-Volatile Memories Using Compressed Address Mapping
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Solution Overview
Problem
Existing wear leveling methods for non-volatile memories, such as flash memory devices, face challenges due to the large overhead of indirection tables required for mapping logical block addresses to physical block addresses, making them impractical for large storage devices like 2 terabyte SSDs.
Innovation Solution
A system and method that uses a non-volatile memory to store cumulative control states for random mappings between physical and logical block addresses, with an access network and a background swap scheduler to translate and swap these addresses, reducing the need for extensive hardware and storage by using bitonic networks and pre-calculated cumulative state values.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If table indirection methods are used to map logical pages to physical pages for wear leveling, then uniform usage of all physical pages is achieved, but significant overhead in table size is incurred
Solution Approach 1:
The patent segments the address mapping function into multiple components: a compression function that maps logical addresses to compressed indices, a separate mapping table that stores only the compressed index to physical page mappings, and a decompression function. This segmentation reduces the mapping table size from proportional to total logical pages to proportional to physical pages only, enabling wear leveling on large storage devices without excessive overhead
Solution Approach 2:
The patent extracts the frequently accessed mapping information (physical page assignments) from the complete logical-to-physical mapping table, storing only these essential mappings in a compact table. The compression and decompression functions handle the translation of logical addresses to these stored mappings, eliminating the need to store mappings for all possible logical addresses
2Reliability
If a 137 GB table is used for a 2 TB storage device to track frequency of use for all logical pages, then wear leveling can be performed, but the table size becomes impractical
Solution Approach 1:
The patent changes the parameter representation by introducing compression functions that transform logical address parameters into compact index parameters. Instead of storing mappings for all possible logical addresses (requiring 137 GB), the system stores mappings only for physical pages using compressed indices, reducing the table size to a practical magnitude while preserving wear leveling functionality
Solution Approach 2:
The patent creates a compressed representation (copy) of the address mapping information that retains the essential wear leveling data. The compression function generates a condensed version of the mapping relationships that can be expanded back to full mappings when needed, allowing the system to work with much smaller table structures
Data Source
AI summary
Systems and methods for wear leveling in non-volatile memories (NVMs) are illustrated. One such system includes a first non-volatile memory configured to store information from a host, a second non-volatile memory storing a plurality of cumulative control states, each indicative of a state of random mappings between physical block addresses (PBAs) and logical block addresses (LBAs) of the first non-volatile memory, and a plurality of control states, an access network configured to translate LBAs to PBAs based on the plurality of cumulative control states, a background swap scheduler configured to swap PBAs assigned to LBAs based on the plurality of control states, and a controller configured to sequentially advance through the plurality of cumulative control states and the plurality of control states.