Variable Threshold Wear Leveling for Non-Volatile Memory
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Solution Overview
Problem
Wear leveling mechanisms in non-volatile memory devices face challenges in balancing even erase operations across blocks, leading to reduced system performance and product lifetime due to frequent data exchanges and increased erase counts.
Innovation Solution
A method that dynamically adjusts the wear leveling limit and erase count threshold based on the stage of the non-volatile memory's lifespan, starting with a larger limit and gradually reducing it, to control the frequency and amount of wear leveling operations, thereby extending the device's lifespan.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wear leveling is performed frequently to maintain even erase counts across blocks, then the difference in erase counts between blocks is reduced, but system performance deteriorates and product lifetime is reduced due to increased overall erase count
Solution Approach 1:
The patent applies dynamics by making the wear leveling limit variable rather than fixed. The wear leveling limit is dynamically adjusted based on the current erase count of blocks, allowing the system to adapt its wear leveling behavior to the actual state of the memory device. This resolves the contradiction by enabling frequent wear leveling when needed (to maintain evenness) while reducing unnecessary wear leveling operations when the limit would be exceeded, thereby preserving system performance and extending product lifetime.
2Reliability
If wear leveling limit is reduced to maintain tighter erase count distribution, then erase count evenness is improved, but the frequency of wear leveling operations increases which reduces product lifetime
Solution Approach 1:
The patent dynamically adjusts the wear leveling limit based on the current erase count state of the memory blocks. When blocks have low erase counts, a larger wear leveling limit is allowed, reducing the frequency of wear leveling operations. When blocks approach higher erase counts, the limit is reduced to maintain evenness. This dynamic adjustment resolves the contradiction by optimizing the balance between erase count evenness and product lifetime throughout the device's operational life.
Solution Approach 2:
The patent changes the parameter of wear leveling limit based on the operational stage of the memory device. By monitoring the erase count and determining the current stage, the system adjusts the wear leveling limit parameter accordingly. This parameter change strategy allows the system to maintain reliable erase count distribution while minimizing the total number of wear leveling operations, thereby extending product lifetime.
3Reliability
If wear leveling is performed to extend memory life by distributing erase operations evenly, then block-level reliability is improved, but overall device lifetime is reduced due to increased total erase operations
Solution Approach 1:
The patent implements dynamic adjustment of the wear leveling limit based on the current erase count distribution across blocks. This dynamic approach ensures that wear leveling operations are performed only when necessary to maintain evenness, rather than following a fixed schedule or fixed limit. Consequently, the system achieves reliable block-level erase distribution while minimizing unnecessary operations that would reduce overall device lifetime.
Solution Approach 2:
The patent changes the wear leveling limit parameter according to the operational stage determined by the highest erase count. In early stages with low erase counts, a larger limit is applied, reducing operation frequency. As the device ages and erase counts increase, the limit is reduced to maintain evenness. This staged parameter adjustment resolves the contradiction by adapting the wear leveling strategy to the device's lifecycle, preserving both block-level reliability and overall device lifetime.
Data Source
AI summary
A wear leveling limit and/or an overall erase count threshold used for activating wear leveling in a non-volatile memory may be adjusted by determining a stage according to a highest erase count, and determining the wear leveling limit and/or the overall erase count threshold corresponding to the stage. Wear leveling may then be performed according to the wear leveling limit and/or the overall erase count threshold.