Neural Network Weight Calibration for CMOS Peripheral Variability
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Solution Overview
Problem
Neural networks (NNs) encoded in hardware chips with Non-Volatile Memories (NVMs) face significant CMOS peripheral variability, leading to degraded evaluation of ΣWx Multiply-Accumulate operations due to unaddressed sources like current mirror mismatch.
Innovation Solution
A computer-implemented method for balancing neural network weight asymmetries by programming major and minor conductance pairs using closed-loop tuning to force an inference output to an expected duration value, compensating for column-to-column variability through mismatch evaluation and incremental programming of conductance pairs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing calibration methods are used to address CMOS peripheral variability, then some variability is reduced, but current mirror mismatch and other sources of variability remain unaddressed
Solution Approach 1:
The patent segments the weight encoding into multiple conductance pairs (major positive, major negative, minor positive, minor negative) distributed across multiple devices. This segmentation allows independent calibration of each pair to compensate for different sources of variability, with major pairs handling column-to-column variation and minor pairs addressing current mirror mismatch.
Solution Approach 2:
The patent changes the parameters of conductance pairs through calibration processes. Target weights are adjusted based on measured variability characteristics, and conductance values are programmed to specific target values that compensate for peripheral asymmetries. This parameter adjustment enables the system to adapt to manufacturing variations and peripheral variability.
2Measurement precision
If multiple devices are assigned to each weight with variable distribution, then weight precision is improved, but peripheral variability degrades the multiply-accumulate operation
Solution Approach 1:
The patent implements feedback through calibration procedures where the actual conductance values are measured, compared against target values, and adjusted accordingly. The calibration process uses feedback from variability measurements to determine mismatch values that are applied to counteract fixed peripheral asymmetries, ensuring accurate multiply-accumulate operations despite peripheral variability.
Solution Approach 2:
The patent intentionally introduces asymmetry in the form of mismatch values that are applied differently to major and minor conductance pairs. These asymmetric adjustments compensate for the inherent asymmetries in CMOS peripheral circuits, such as current mirror mismatch, allowing the system to achieve symmetry in the overall weight representation despite peripheral imperfections.
3Reliability
If calibration is applied to reduce variability, then inference accuracy is improved, but additional circuit overhead is introduced
Solution Approach 1:
The patent uses the same NVM devices to serve multiple functions: storing weights during normal operation and participating in calibration procedures for variability compensation. The major and minor conductance pairs are integrated into the existing weight storage architecture, eliminating the need for separate calibration circuits and reducing overall device complexity.
Solution Approach 2:
The calibration process is self-performed by the NVM devices themselves through programming operations that adjust their own conductance values. The system uses its existing programming capabilities to set conductance pairs to target values, eliminating the need for external calibration equipment or additional control circuitry.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances resilience to CMOS peripheral variability without adding circuit overhead, effectively counteracting fixed asymmetries and improving neural network performance.
Implementation Method 1
programming the one or more major conductance pairs to force an inference output to an expected duration value
Implementation Method 2
programming the one or more minor conductance pairs to force the inference output to the expected duration value
Data Source
AI summary
Embodiments herein disclose computer-implemented methods, computer program products and computer systems for balancing neural network weight asymmetries. The computer-implemented method may include providing a neural network with weights comprising one or more major conductance pairs and one or more minor conductance pairs. The method may further include programming the one or more major conductance pairs to force an inference output to an expected duration value, determining a positive weight coefficient based on the one or more major conductance pairs and a negative weight coefficient based on the one or more minor conductance pairs, determining one or more target weights based on one or more of the positive weight coefficient and the negative weight coefficient, programming the one or more minor conductance pairs to force the inference output to the expected duration value, and programming the one or more major conductance pairs with the one or more target weights.