Weight Memory Device Voltage Readout for Low-Power Neural Networks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional neuromorphic technologies face challenges in reducing power consumption during readout processes due to continuous DC current flow, require complex timing control, and have increased manufacturing costs and complexity, especially when implementing memristor processes and peripheral circuits.
Innovation Solution
A weight memory device that detects voltage differences instead of current, utilizing a charge storage structure with capacitance-based data storage and built-in MAC operation, optimized for artificial neural networks, allowing for reduced power consumption and simplified manufacturing processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If voltage is used as input and current is used as output in conventional neuromorphic systems, then MAC operation is naturally achieved, but continuous DC current flows during readout process increasing power consumption
Solution Approach 1:
The patent changes the output parameter from current to voltage. The memory cell outputs voltage instead of current, and the readout circuit detects voltage differences. This parameter change eliminates the need for continuous DC current flow while maintaining MAC operation capability, directly resolving the power consumption issue.
Solution Approach 2:
The patent employs periodic pulse signals for writing and reading operations instead of continuous current flow. The readout circuit uses periodic clock signals to sample voltage differences at specific timing, which simplifies timing control compared to maintaining continuous DC current while still achieving the desired MAC operation.
2Reliability
If memristor process and peripheral circuits are implemented in conventional neuromorphic systems, then weight storage function is achieved, but manufacturing cost and complexity increase
Solution Approach 1:
The patent makes the memory cell structure universal by using standard CMOS-compatible transistor and capacitor configurations that can serve multiple functions: weight storage, MAC operation, and voltage output. This eliminates the need for specialized memristor processes while maintaining weight storage capability, directly addressing the manufacturing complexity issue.
Solution Approach 2:
The memory cell structure is designed to be self-sufficient, performing MAC operation and voltage output inherently through its basic transistor-capacitor configuration without requiring additional specialized peripheral circuits. This self-service capability reduces manufacturing complexity while maintaining reliable weight storage function.
3Ease of operation
If capacitor for integration is used in transfer function circuit, then output transfer is achieved, but area increases and power consumption increases
Solution Approach 1:
The patent merges the weight storage function and the integration function into a single memory cell structure. The capacitor that was previously a separate integration component is integrated into the memory cell itself, eliminating the need for additional discrete capacitors and reducing overall circuit area while maintaining the transfer function capability.
Solution Approach 2:
The memory cell is designed with multi-functionality, serving both as weight storage element and as integration element for the transfer function. This universal design eliminates the need for separate dedicated integration capacitors, reducing area occupation while maintaining output transfer capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables low-power operation, reduced area occupation, and increased integration by eliminating the need for constant DC current, simplifying timing control, and leveraging conventional semiconductor processes, while supporting rapid artificial neural network operations and various network configurations.
Implementation Method 1
charge storage disposed between the input terminal and the common output terminal, and configured to store charge. The capacitance between the input terminal and the common output terminal is determined based on the amount of charge stored in the charge storage
Implementation Method 2
A weight memory device that detects voltage differences instead of current, utilizing a charge storage structure with capacitance-based data storage
Data Source
AI summary
Disclosed are a weight memory device capable of supporting artificial neural network operation and a weight memory system using the same. A weight memory device according to an embodiment of the present invention includes: an input terminal; a common output terminal; and charge storage disposed between the input terminal and the common output terminal, and configured to store charge. In this case, the capacitance between the input terminal and the common output terminal is determined based on the amount of charge stored in the charge storage, and is quantified based on given data to be stored in the weight memory device.