Weight Remapping Circuit for Transposed CIM MAC Operations
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Solution Overview
Problem
The computational bottleneck in machine learning systems due to the transfer of large data elements between processor and memory resources, and the inefficiency of conventional computing-in-memory (CIM) circuits in performing MAC operations with rearranged weight feature maps.
Innovation Solution
A CIM circuit that performs MAC operations with rearranged weight feature maps without additional cycles and buffers by using enable and address signals to access memory arrays based on both the original and transposed weight matrices, enabling flexible and efficient in-memory computations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data elements are transferred between processor and memory resources, then computational tasks can be performed, but the transfer of large data elements creates a computational bottleneck and increases energy consumption
Solution Approach 1:
The patent combines memory storage and computational processing into a single integrated structure. Memory cells store weight values and simultaneously perform multiply-accumulate operations when activated by input signals, eliminating the need to transfer data between separate processor and memory resources. This merging of storage and computation functions resolves the bottleneck caused by data transfer between discrete components.
Solution Approach 2:
The patent introduces sense amplifiers as intermediary components that facilitate computation within the memory array. These amplifiers receive input signals, interact with stored weight values in memory cells, and produce output signals representing computational results. This intermediary mechanism enables in-memory computing without requiring traditional processor-memory data transfer, thereby reducing energy consumption while maintaining computational throughput.
2Productivity
If conventional CIM circuits are used to perform MAC operations, then in-memory computation is achieved, but additional cycles and buffers are required which reduce computational efficiency
Solution Approach 1:
The patent segments the memory array into multiple independently controllable banks or regions, each capable of performing MAC operations. By dividing the memory into smaller functional units with dedicated sense amplifiers and control logic, the system can perform computations directly within memory segments without requiring additional global buffers or multiple sequential cycles. This segmentation enables efficient in-memory computing while reducing the complexity overhead of conventional CIM approaches.
Data Source
AI summary
A circuit for weight mapping for a computation in memory circuit includes memory cells, first address lines, each coupled with a corresponding one of the memory cells, and second address lines, each coupled with a set of cells in the memory cells. One or more cells in the memory cells are configured to be accessed for one or more weight values, when one or more of the first address lines and one or more of the second address lines corresponding to the one or more cells in the memory cells are asserted. The one or more cells that are accessed at a first time correspond to a first weight matrix, and the one or more cells that are accessed at a second time correspond to a second weight matrix, the second weight matrix being a transposed one of the first weight matrix.