Weighted Age Arbitration for Shared Memory Fabric Fairness

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Solution Overview

Problem

Current computer systems with shared resources, such as memory, face issues with unfair access allocation and power management, leading to starvation and inefficiency due to fixed priority arbitration and lack of consideration for power states in resource access.

Innovation Solution

A shared memory fabric with a weighted age-based arbitration method and virtual channels to prioritize real-time and auxiliary traffic, using request deadlines and power state management to ensure predictable and efficient memory bandwidth allocation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If fixed priority arbitration is used to allocate access to shared memory, then access allocation is simplified, but fairness deteriorates and starvation occurs

Engineering Contradiction:
Improvearbitration mechanism complexityVSAvoidaccess fairness
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The arbitration mechanism dynamically adjusts priority based on agent state (awake/sleep) and request characteristics. The arbiter transitions from static fixed priority to dynamic priority assignment, where priorities are modified according to current system conditions, preventing starvation while maintaining manageable complexity

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system changes the priority parameter based on agent power state and request type. When an agent is awake and has pending requests, its priority is elevated; when sleeping, priority is reduced. This parameter transformation resolves the contradiction by making priority adaptive rather than fixed

Inventive Principle:
Principle #35Parameter changes

2Reliability

If round robin arbitration is used to allocate access to shared memory, then fairness is improved, but access efficiency deteriorates due to unnecessary wake-ups

Engineering Contradiction:
Improveaccess fairnessVSAvoidmemory access efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

Different arbitration strategies are applied to different agents based on their local state. Awake agents receive preferential treatment through elevated priority, while sleeping agents are handled differently. This localized quality adjustment ensures fairness for active agents without forcing unnecessary wake-ups, maintaining both fairness and efficiency

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The system performs preliminary checking of agent power state before granting memory access. By checking whether agents are awake or sleeping prior to arbitration, the system可以避免 waking sleeping agents unnecessarily, thus maintaining efficiency while still providing fair access to awake agents

Inventive Principle:
Principle #10Preliminary action

3Speed

If memory access is granted without considering power state, then response time is reduced, but power consumption increases due to unnecessary state transitions

Engineering Contradiction:
Improvememory access response timeVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The arbitration system incorporates feedback from agent power state monitoring. The arbiter continuously receives information about whether agents are awake or sleeping and adjusts arbitration decisions accordingly. This feedback loop ensures that memory access is granted efficiently to awake agents while avoiding unnecessary wake-ups of sleeping agents, balancing response time and power consumption

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The system performs preliminary assessment of agent power state before initiating memory access operations. By checking the power state in advance, the system can grant immediate access to awake agents (maintaining fast response time) while keeping sleeping agents in low-power state (reducing power consumption), thus resolving the contradiction

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10133670B2Low overhead hierarchical connectivity of cache coherent agents to a coherent fabric
Publication Date: 2018.11.20 INTEL CORP
  • US10133670B2 patent drawing
  • US10133670B2 patent drawing
  • US10133670B2 patent drawing

AI summary

In an example, a system-on-a-chip comprises a plurality of multi-core processors, such as four dual-core processors for eight total cores. Each of the processors connects to shared resources such as memory and peripherals via a shared uncore fabric. Because each input bus for each core can include hundreds of data lines, the number of lines into the shared uncore fabric can become prohibitive. Thus, inputs from each core are multiplexed, such as in a two-to-one configuration. The multiplexing may be a non-blocking, queued (such as FIFO) multiplexing to ensure that all packets from all cores are delivered to the uncore fabric. In certain embodiment, some smaller input lines may be provided to the uncore fabric non-multiplexed, and returns (outputs) from the uncore fabric to the cores may also be non-multiplexed.