Weighted-Bit RF Attenuator and Phase Shifter for Finer Steps
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Solution Overview
Problem
Existing digital step attenuators (DSA) and phase shifters have limited resolution, which restricts their accuracy in RF applications, and require a large number of stages and control lines, increasing cost and complexity.
Innovation Solution
The use of dithering approaches to weight bits in DSA and DPS circuits, allowing for higher resolution and finer fractional intermediate steps of attenuation or phase shift, achieved through bit position weighting functions such as linear, alternating linear, geometric, alternating geometric, harmonic, and alternating harmonic series, enabling a higher range-to-resolution ratio and improved Figure of Merit (FOM) without additional cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional binary-weighted attenuator stages are used, then the DSA can achieve basic attenuation functionality, but the resolution is limited and requires a large number of stages and control lines
Solution Approach 1:
The patent applies parameter changes by using non-binary weighting schemes (ternary, quaternary, quintary) instead of conventional binary weighting. This changes the fundamental parameter of bit weight assignment, allowing each control line to represent multiple attenuation levels (e.g., 0, 1, 2 dB for ternary) rather than just two states. This parameter change enables higher resolution with fewer stages and control lines, directly resolving the technical contradiction between attenuation resolution and device complexity
Solution Approach 2:
The patent segments the attenuation range into smaller discrete steps using weighted bits. By dividing the total attenuation range into fine-grained segments (e.g., 0.5 dB or 1 dB steps) through clever bit weighting, the system achieves high resolution without requiring a proportional increase in the number of attenuator stages. Each bit position is segmented to control specific attenuation increments, reducing the overall number of control lines needed
2Measurement precision
If more attenuator stages are added to increase resolution, then attenuation precision improves, but the device complexity and cost increase
Solution Approach 1:
The patent changes the weighting parameter from binary (2 states per bit) to higher-base systems (3, 4, or 5 states per bit). This parameter change allows each additional control line to provide disproportionately more resolution than conventional binary systems. For example, a ternary system provides 1.58 times more resolution per control line than binary, reducing the total number of control lines and attenuator stages needed, thereby lowering manufacturing cost while maintaining or improving resolution
3Adaptability or versatility
If binary-weighted stages are used, then the circuit design is simple, but the range-to-resolution ratio is limited
Solution Approach 1:
The patent changes the bit position weighting parameter from binary to higher-base weighting schemes. This enables the system to achieve a superior range-to-resolution ratio because each control line can represent multiple attenuation levels. The versatility is enhanced as the same hardware architecture can be configured for different weighting schemes (ternary, quaternary, quintary) to match different application requirements, while the bit position weighting complexity is managed through systematic design methods
Data Source
AI summary
Digital step attenuator (DSA) and digital phase shifter (DPS) multi-stage circuit architectures that provide for high resolution. Embodiments use a dithering approach to weight bit positions to provide a much finer resolution than the lowest-valued individual stage. Bit position weights for stages are determined so as to enable selection of combinations of n bit positions that provide a desired total attenuation or phase shift range while allowing utilization of the large number of states (2n) available to produce fractional intermediate steps of attenuation or phase shift. The fractional intermediate steps have a resolution finer than the lowest-valued stage. Bit position weights may be determined using a weighting function, including weightings determined from a linear series, a geometric series, a harmonic series, or alternating variants of such series. In some embodiments, at least one bit position has a fixed value that is not determined by the bit position weighting function.