Weighted Interpolation Converter for Matched Differential Clocks
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Converting single-ended signals to differential signals in high-speed ICs, such as DDR memory and SerDes, is challenging due to difficulties in matching delays and duty cycles of differential output clock signals, leading to inefficiencies and noise immunity issues.
Innovation Solution
A single-ended to differential signal converter is designed with a chain of inverting elements of varying sizes, including programmable current conducting legs and capacitors, to ensure matching delays and duty cycles through weighted interpolation and calibration, forming a symmetrical structure to address layout and manufacturing variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional single-ended to differential signal conversion is used in high-speed ICs, then the conversion can be implemented with simple circuitry, but the delays and duty cycles of the differential output clock signals cannot be properly matched
Solution Approach 1:
The converter circuit is divided into multiple independent inverting elements (first through seventh inverters) with different sizes, where each element contributes a specific delay component. This segmentation allows independent optimization of delay characteristics for each element to achieve precise delay matching between differential signals.
Solution Approach 2:
Different inverting elements are designed with different sizes (first size for inverters 1-3, second size for inverters 4 and 7, third size for inverters 5 and 6) to create local variations in delay characteristics. This local quality differentiation enables precise control over the delay and duty cycle of each signal path to achieve overall signal matching.
2Manufacturing precision
If the converter uses inverting elements of different sizes to achieve weighted interpolation, then accurate delay and duty cycle matching is achieved, but the circuit design and manufacturing complexity increases
Solution Approach 1:
The inverting elements are designed with different size parameters (transistor widths, lengths, or gate areas) to create distinct delay characteristics. By carefully selecting these physical parameters, the circuit achieves weighted interpolation of delay values, enabling precise duty cycle and delay matching without requiring complex external adjustment mechanisms.
3Reliability
If symmetrical structure is used to address layout and manufacturing variations, then signal matching is improved, but the device area and complexity increase
Solution Approach 1:
While the overall converter structure is symmetrical to address layout variations, the individual inverting elements within each half are deliberately asymmetric in size (different first, second, and third sizes). This controlled asymmetry enables precise delay matching within each differential signal path, while the outer symmetry maintains robustness against manufacturing variations.
Data Source
AI summary
A single-ended to a differential signal converter (converter) includes, in part, first, second, and third inverting elements, each having a first size, and coupled in series to form a chain of inverting elements. The converter further includes a fourth inverting element of a second size and coupled to the input of the first inverting element, a fifth inverting element of a third size and coupled to an output terminal of the first inverting element, a sixth inverting element of the third size and coupled to an output of the second inverting element, and a seventh inverting element of the second size and coupled to the output of the third inverting element. The outputs of the fourth and sixth inverting elements form a first one of the differential signals. The outputs of the fifth and seventh inverting elements form a second one of the differential signals.