Weighted-Summation DAC Circuit for 12-Bit Offset Calibration
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Solution Overview
Problem
Conventional digital-to-analog converters face challenges in achieving high accuracy for 8K displays requiring 12-bit digital-to-analog conversion, particularly with offset voltage issues affecting the buffer operational amplifier.
Innovation Solution
A digital-to-analog conversion circuit comprising a first and second sub-circuit with weighted summation operational amplifiers, switching control modules, and energy storage modules, which perform offset voltage calibration and digital-to-analog conversion stages to accurately convert binary digital signals into analog voltages, addressing the offset voltage challenge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional digital-to-analog converters are used for 12-bit conversion, then basic conversion function is provided, but conversion accuracy is insufficient due to offset voltage issues
Solution Approach 1:
The patent applies preliminary action by performing offset voltage calibration before the actual digital-to-analog conversion. The buffer operational amplifier undergoes offset voltage calibration in a first time period, and the digital-to-analog conversion is performed in a second time period. This preliminary calibration eliminates offset voltage errors before conversion, ensuring high accuracy for 12-bit conversion without compromising reliability.
Solution Approach 2:
The patent implements feedback by using the buffer operational amplifier to provide feedback signals during the calibration process. The feedback mechanism allows the system to detect and compensate for offset voltage errors, thereby improving conversion accuracy while maintaining stable operation throughout the conversion process.
2Measurement precision
If high-accuracy 12-bit digital-to-analog conversion is implemented, then conversion precision is improved, but power consumption increases
Solution Approach 1:
The patent applies periodic action by dividing the operation into distinct time periods: a first time period for offset voltage calibration and a second time period for digital-to-analog conversion. This periodic structure allows the buffer operational amplifier to operate at high precision during conversion while consuming minimal power during calibration, thereby achieving high conversion precision without significant power consumption increases.
Solution Approach 2:
The patent segments the conversion process into separate functional stages handled by different sub-circuits. The first digital-to-analog conversion sub-circuit handles most significant bits, while the second sub-circuit handles least significant bits with weighted summation. This segmentation enables each segment to operate optimally with appropriate power levels, achieving overall high precision without excessive total power consumption.
Data Source
AI summary
A digital-to-analog conversion circuit, a digital-to-analog conversion method, and a display device are provided. The digital-to-analog conversion circuit includes a first digital-to-analog conversion sub-circuit and a second digital-to-analog conversion sub-circuit. The second digital-to-analog conversion sub-circuit includes least-significant-bit voltage selection modules whose quantity is a, a weighed summation operational amplifier, switching control modules whose quantity is a and energy storage modules whose quantity is a. The weighted summation operational amplifier includes a reverse-phase input end, an operational amplification output end, and same-phase input ends whose quantity is a. The reverse-phase input end is connected to the operational amplification output end, and a is an integer greater than 1. The weighted summation operational amplifier is configured to perform weighted summation on voltages inputted by the a same-phase input ends at a digital-to-analog conversion stage to acquire an analog voltage, and output the analog voltage via the operational amplification output end.