Memory Subsystem QoS via Weighted I/O Prioritization

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Solution Overview

Problem

Conventional memory sub-systems face challenges in providing consistent Quality of Service (QoS) levels to multiple functions, particularly in NAND-based memory devices, where write operations are slow and asynchronous, interfering with incoming system I/Os, and background operations like garbage collection can unpredictably impact I/O performance.

Innovation Solution

The memory sub-system assigns function weights and operation weights to prioritize I/O operations, implementing a program/erase suspend/resume policy to manage QoS levels, ensuring predictable processing times and latency by differentiating between read and write operations and handling background operations effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If write operations are performed in NAND-based memory devices, then data storage capability is improved, but I/O performance and system responsiveness deteriorate due to slow and asynchronous write operations

Engineering Contradiction:
Improvedata storage capabilityVSAvoidI/O performance
Core Design Contradiction:
ReliabilityVSSpeed

Solution Approach 1:

The patent segments I/O operations into different types (read, write, background operations) and assigns different weights to each type. This segmentation allows the system to prioritize read operations and important write operations while managing background operations separately, thereby improving overall I/O performance while maintaining data storage capability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent changes the parameter of operation priority by assigning weights to different operation types. By dynamically adjusting these weights, the system can optimize I/O performance for different workloads while ensuring data storage reliability is maintained through appropriate handling of write operations.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If background operations like garbage collection are performed, then memory maintenance and data integrity are improved, but I/O performance becomes unpredictable due to interference with incoming system I/Os

Engineering Contradiction:
Improvedata integrityVSAvoidI/O performance predictability
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by assigning weights to background operations beforehand, allowing the system to pre-determine their priority relative to incoming I/O operations. This enables predictable I/O performance while ensuring necessary memory maintenance operations are performed.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent introduces an intermediary mechanism (weight-based priority system) that mediates between background operations and incoming I/O operations. This intermediary allows the system to balance memory maintenance requirements with I/O performance predictability by controlling when and how background operations interfere with system I/Os.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Productivity

If multiple functions share the same memory sub-system without differentiation, then resource utilization is improved, but Quality of Service levels cannot be consistently provided to different functions

Engineering Contradiction:
Improveresource utilizationVSAvoidQuality of Service consistency
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent applies local quality by assigning different weights to different functions and operation types within the same memory sub-system. This allows each function to receive appropriate QoS levels based on its specific requirements while maintaining high overall resource utilization through shared infrastructure.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS11687244B2Quality of service for memory devices using weighted memory access operation types
Publication Date: 2023.06.27 MICRON TECHNOLOGY INC
  • US11687244B2 patent drawing
  • US11687244B2 patent drawing
  • US11687244B2 patent drawing

AI summary

A processing device, operatively coupled with the memory device, is configured to provide a plurality of functions for accessing the memory device, a function of the plurality of functions receives input/output (I/O) operations from a host computing system. The processing device further selects a first function of the plurality of functions to service and assigns a first operation weight to a first I/O operation type of I/O operations received at the first function and a second operation weight to a second I/O operation type of I/O operations received at the first function. The processing device also selects, for execution, a first number of operations of the first I/O operation type of the I/O operations received at the first function according to the first operation weight and a second number of operations of the second I/O operation type of the I/O operations received at the first function according to the second operation weight. The processing device then executes the first number of operations and the second number of operations at the memory device.