Circuit Self-Test With Weighted LFSR Pattern Modification
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Solution Overview
Problem
As semiconductor integration and complexity increase, scan-based tests require more scan cells, leading to increased test data volume, time, and costs, with reduced failure detection probability due to ineffective data and higher power consumption.
Innovation Solution
A circuit self-test apparatus using a test circuit with a linear feedback shift register (LFSR) generates random patterns for scan chains, modifying them based on scan cell weights and correlations to reduce test data and power consumption while enhancing defect detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If scan-based test is used to detect defects in larger circuits, then defect detection capability is improved, but test data volume and test time increase rapidly
Solution Approach 1:
The patent extracts and removes ineffective test data from the test sequence. By analyzing scan chain characteristics and identifying redundant patterns, the system extracts only the necessary test data required for defect detection, thereby reducing overall test data volume and test time while maintaining defect detection capability
Solution Approach 2:
The patent changes parameters of test patterns by applying transformation techniques such as inversion, complementation, and permutation to generate diverse test sequences. This allows the same scan chain to be tested with varied patterns, improving defect detection coverage without proportionally increasing test time
2Reliability
If more scan cells are added to detect defects in larger circuits, then defect detection capability is improved, but test data volume increases rapidly
Solution Approach 1:
The patent merges multiple scan chains into groups and applies unified test patterns to entire groups rather than testing each scan chain individually. By combining scan chains with similar characteristics and using group-level test sequences, the system reduces redundant test data while maintaining comprehensive defect detection across all scan cells
Solution Approach 2:
The patent develops universal test patterns that can be applied across multiple scan chains simultaneously. These multi-functional test sequences are designed to detect defects in various scan chain configurations without requiring separate specialized test data for each chain, thereby reducing overall test data volume
3Reliability
If conventional test patterns are used, then test coverage is maintained, but power consumption increases
Solution Approach 1:
The patent implements periodic test patterns that alternate between active testing phases and low-power idle phases. By periodically switching scan chain states and using clock gating techniques during non-critical test intervals, the system maintains required test coverage while significantly reducing average power consumption during test operations
Data Source
AI summary
A circuit self-test apparatus includes a circuit under test including a plurality of scan chains, where each of the plurality of scan chains includes a plurality of scan cells, and where each of the plurality of scan chains are configured based on a weight and a correlation obtained from a determination pattern input into each of the plurality of scan cells, and a test circuit including a linear feedback shift register (LFSR) configured to generate a random pattern for each of the plurality of scan chains, where the test circuit is configured to generate a modification pattern for each of the plurality of scan chains based on the random pattern and a state of the LFSR.