Weighted Summing Phase Interpolator for Clock Linearity
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Solution Overview
Problem
Phase interpolators implemented in transistor circuits suffer from non-linearity, resulting in unequal phase increments between reference clocks, which can lead to data capture errors due to suboptimal synchronization.
Innovation Solution
A weighted summing phase interpolator that combines the outputs of two PI circuits with offset interpolation codes and a weighted summing circuit to generate a clock signal with improved linearity, using a weight signal to balance the influence of the interpolated clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional PI circuit is used to generate interpolated clock, then the device complexity is low, but the phase increments are non-uniform due to transistor non-linearity
Solution Approach 1:
The PI circuit is divided into two separate sub-PI circuits (first PI circuit and second PI circuit), each handling a portion of the interpolation task. This segmentation allows each sub-circuit to be optimized for specific phase ranges, improving overall linearity while keeping individual circuit complexities manageable.
Solution Approach 2:
The outputs of the first and second PI circuits are combined through a summing circuit to produce the final interpolated clock signal. This merging approach allows the benefits of both sub-circuits to be integrated, achieving improved phase uniformity that neither circuit could achieve alone.
2Manufacturing precision
If offset interpolation codes are used in two PI circuits, then the non-linearity is reduced, but the device complexity increases
Solution Approach 1:
Each PI circuit is assigned a specific offset interpolation code range, allowing each circuit to operate optimally within its designated phase region. This local optimization ensures that each circuit handles the interpolation task with reduced non-linearity in its specific operating range.
Solution Approach 2:
The summing circuit acts as an intermediary that combines the outputs of the two PI circuits. This intermediary component facilitates the integration of results from both circuits, producing a final output with improved linearity while managing the complexity introduced by having multiple PI circuits.
3Measurement precision
If weighted summing is applied to combine interpolated clocks, then the phase accuracy is improved, but the device complexity increases
Solution Approach 1:
Weighting factors are applied to the interpolated clock signals from the two PI circuits before summing them. By adjusting these weighting parameters, the contribution of each circuit's output can be optimized to maximize phase accuracy and minimize residual non-linearity in the final combined signal.
Data Source
AI summary
To compensate for the non-linearity of a phase interpolation (PI) circuit, the interpolation clocks of two PI circuits receiving different interpolation codes may be summed. However, even if the non-linearities of the interpolated clocks have opposite polarities, they may have different magnitudes causing some non-linearity. A weighted summing PI that sums interpolated clocks of two PI circuits includes a weighted summing circuit that employs a weight signal to generate a weighted summed interpolated clock having an interpolated phase, based on the weight signal, between the phases of the interpolated clocks. As a result, the phase of the weighted summed interpolated clock may be more influenced by the phase of one of the interpolated clocks from the two PI circuits than the other. A weight calibration circuit may be included to select a balanced weight signal to reduce non-linearity in the weighted summing PI.