Weighted Phase Interpolation Circuit for High Linearity

Solution Overview

Problem

Existing phase interpolation circuits face challenges in achieving high linearity, which is crucial for precise phase adjustment, but increasing the length of the interpolation circuit to improve linearity results in increased chip area and power consumption.

Innovation Solution

A phase interpolation circuit with a high linearity is designed, utilizing multiple phase interpolation units with adjustable weights, where each unit's circuit parameter is optimized to minimize output delay differences, allowing for precise phase control without increasing the circuit length, and incorporating a weight adjustment circuit to compensate for nonlinearity caused by MOS transistors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the length N of the phase interpolation circuit is increased to improve linearity, then phase adjustment precision is improved, but chip area and power consumption increase

Engineering Contradiction:

Improvephase adjustment precisionVSAvoidchip area

Core Design Contradiction:

Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent changes the circuit parameters (transistor widths W1, W2, W3, W4) of the phase interpolation units to compensate for nonlinearity. By optimizing these parameters, the output phases are uniformly distributed without increasing the circuit length N, thus improving phase adjustment precision while maintaining the same chip area.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent applies different circuit parameters to different phase interpolation units based on their position in the circuit. Each unit has locally optimized parameters (different W1, W2, W3, W4 values) to compensate for position-dependent nonlinearity, achieving uniform phase distribution without increasing overall circuit length.

Inventive Principle:

Principle #3Local quality

2Measurement precision

If the length N of the phase interpolation circuit is increased to improve linearity, then phase adjustment precision is improved, but power consumption increases

Engineering Contradiction:

Improvephase adjustment precisionVSAvoidpower consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by stationary object

Solution Approach 1:

The patent changes the circuit parameters (transistor widths W1, W2, W3, W4) of the phase interpolation units to compensate for nonlinearity. By optimizing these parameters, the output phases are uniformly distributed without increasing the circuit length N, thus improving phase adjustment precision while maintaining the same power consumption.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The patent applies different circuit parameters to different phase interpolation units based on their position in the circuit. Each unit has locally optimized parameters (different W1, W2, W3, W4 values) to compensate for position-dependent nonlinearity, achieving uniform phase distribution without increasing overall power consumption.

Inventive Principle:

Principle #3Local quality

3Measurement precision

If the circuit parameters of phase interpolation units are adjusted to compensate for MOS transistor nonlinearity, then output phase uniformity is improved, but device complexity increases

Engineering Contradiction:

Improveoutput phase uniformityVSAvoidcircuit parameter configuration

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent changes the circuit parameters (transistor widths W1, W2, W3, W4) of the phase interpolation units to compensate for nonlinearity. The method provides a systematic approach to parameter optimization that improves output phase uniformity while keeping the circuit structure itself simple and manageable.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS11791827B2Phase interpolation circuit with high linearity

Publication Date: 2023.10.17 WUXI ESIONTECH CO LTD

AI summary

A phase interpolation circuit with a high linearity includes a first parallel circuit constituted by M phase interpolation units, and a second parallel circuit constituted by N phase interpolation units. An input terminal of the first parallel circuit is connected to a first clock input terminal and grounded via a first capacitor. An input terminal of the second parallel circuit is connected to a second clock input terminal and grounded via a second capacitor. An output terminal of the first parallel circuit and an output terminal of the second parallel circuit are connected to a clock output terminal and grounded via a zeroth capacitor. A circuit parameter of each phase interpolation unit corresponds to a target output weight respectively. The target output weight of each phase interpolation unit is determined by iteration to minimize a phase difference between all output clock signals of the phase interpolation circuit.