Weighted Wear Leveling for Memory Cell Uniformity

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Solution Overview

Problem

Existing memory devices face non-uniform threshold voltage distributions due to varying electrical distances from voltage sources, leading to uneven degradation and error rates, which conventional wear leveling and seasoning techniques fail to adequately address.

Innovation Solution

Implementing weighted wear leveling by grouping memory cells based on electrical distance and assigning a proportional share of write operations to counteract higher degradation at near electrical distances, dynamically adjusting shares based on temperature, write operations, and error correction codes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If memory cells are uniformly distributed without weighting, then device complexity is low, but threshold voltage uniformity deteriorates due to varying electrical distances from voltage sources

Engineering Contradiction:
Improvethreshold voltage uniformityVSAvoidwear leveling complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent applies local quality by dividing memory cells into different groups based on their electrical distance from voltage sources. Each group receives a customized weight factor that reflects its specific degradation characteristics. This allows the wear leveling algorithm to tailor its approach to local conditions rather than applying a uniform distribution strategy across all memory cells.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent segments the memory cell population into multiple groups based on electrical distance metrics. By segmenting the memory space and applying different weight factors to different segments, the system achieves better threshold voltage uniformity while managing complexity through structured organization rather than treating all cells equally.

Inventive Principle:
Principle #1Segmentation

2Reliability

If weighted wear leveling is implemented to improve uniformity, then threshold voltage distribution improves, but device complexity increases due to dynamic adjustment mechanisms

Engineering Contradiction:
Improvememory device enduranceVSAvoidwear leveling mechanism complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements feedback mechanisms that monitor temperature, write operation counts, and error correction code performance. These feedback signals dynamically adjust the weight factors assigned to different memory cell groups, allowing the system to adapt to changing conditions and optimize reliability while managing complexity through intelligent control.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent introduces dynamics by making weight factors adjustable rather than fixed. The system dynamically modifies weight assignments based on real-time conditions such as temperature variations and wear patterns, enabling the wear leveling mechanism to respond to changing operational conditions and improve overall device endurance.

Inventive Principle:
Principle #15Dynamics

3Ease of operation

If equal share of write operations is assigned to all memory cells, then ease of operation is high, but degradation uniformity worsens due to position-dependent electrical characteristics

Engineering Contradiction:
Improvewrite operation distribution simplicityVSAvoiddegradation uniformity
Core Design Contradiction:
Ease of operationVSStability of the object's composition

Solution Approach 1:

The patent replaces the simple equal-share approach with a local quality-based distribution strategy. Memory cells closer to voltage sources receive different weight factors than those farther away, compensating for position-dependent electrical characteristics and achieving more uniform degradation patterns across the memory device.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS20240096433A1Weighted wear leveling for improving uniformity
Publication Date: 2024.03.21 MICRON TECHNOLOGY INC
  • US20240096433A1 patent drawing
  • US20240096433A1 patent drawing
  • US20240096433A1 patent drawing

AI summary

A memory device can include multiple memory cells and a processing device operatively coupled with the memory device to perform operations including grouping the memory cells into a groups based on a metric reflecting an electrical distance of a memory cell from a voltage source, and determining, for each group, a respective share of write operations, wherein the share of write operations is related to an aggregate value of the metric for memory cells of the group. The operations can also include distributing the write operations to each group according to the share of write operations determined for the group.