Segmented Weighting Resistor DAC for Fewer Parasitic Nodes
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Solution Overview
Problem
Conventional digital-to-analog converters (DACs) based on resistors require a large range of resistor values for high resolution, leading to a large physical size and increased parasitic nodes, which affects the dynamic behavior of the converter.
Innovation Solution
The proposed solution involves a digital-to-analog conversion circuitry with a weighting resistor circuit comprising three resistive sub-circuits, where the second sub-circuit has a resistivity equal to or smaller than the first, allowing for efficient scaling with fewer unit resistors, reducing the number of parasitic capacitances and silicon area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional scaling approaches are used to achieve high DAC resolution, then the required resistor value range increases, but the physical dimension of the DAC becomes larger and the number of parasitic nodes increases
Solution Approach 1:
The weighting resistor circuit is segmented into multiple sub-circuits (first, second, and third sub-circuits) with different resistivity ranges. Each sub-circuit handles a specific portion of the resistor value range, allowing high-resolution DAC conversion to be achieved without requiring a single large-range resistor that would occupy excessive physical space.
Solution Approach 2:
Different sub-circuits are assigned different resistivity characteristics tailored to their specific function within the DAC. The first sub-circuit has higher resistivity for MSB weights, while the second sub-circuit has lower resistivity for LSB weights. This local optimization of resistivity values allows compact design while maintaining high resolution.
2Measurement precision
If conventional scaling approaches are used to achieve high DAC resolution, then the required resistor value range increases, but the number of parasitic nodes increases which alters the dynamic behavior
Solution Approach 1:
By dividing the weighting resistor circuit into three sub-circuits with clearly defined resistivity ranges, the patent reduces the total number of discrete resistors needed compared to conventional approaches. This segmentation strategy minimizes the number of parasitic nodes while maintaining the ability to achieve high DAC resolution through coordinated operation of the sub-circuits.
3Measurement precision
If a big range in resistor values is required for high DAC resolution, then conventional scaling approaches result in very different implementations of the weighting resistors, but this increases the device complexity
Solution Approach 1:
Each sub-circuit is designed with resistivity values optimized for its specific weight range. The first sub-circuit uses higher resistivity values for MSB weights, the second sub-circuit uses lower resistivity values for LSB weights, and the third sub-circuit provides intermediate values. This local quality approach allows each sub-circuit to be implemented with uniform, manageable resistor values rather than requiring vastly different resistor implementations across the entire DAC.
Data Source
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AI summary
Circuitry for digital-to-analog conversion is provided. The circuitry includes a driver circuit and a weighting resistor circuit coupled to an output of the driver circuit. The weighting resistor circuit includes a first resistive sub-circuit coupled to the output of the driver circuit and an intermediate node. The weighting resistor further includes a second resistive sub-circuit coupled to the intermediate node and a common node. Further, the weighting circuit includes a third resistive sub-circuit coupled to the intermediate node and an output of the circuitry. The resistivity of the second resistive sub-circuit is equal to or smaller than the resistivity of the first resistive sub-circuit.