Well-Biasing Circuit for IC Leakage Reduction
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Solution Overview
Problem
Existing well-biasing circuits for integrated circuits (ICs) face challenges in reducing leakage currents during low power modes, as they either consume excessive power with high-voltage MOS switches or become unreliable with low-voltage MOS switches that fail to track well-bias voltages.
Innovation Solution
The proposed well-biasing circuit includes a well-bias regulator, a switch, and a CMOS inverter that enables and disables the switch based on the operating mode, using low-voltage MOS switches that accurately track well-bias voltages, ensuring complete disconnection of well contacts from power supply or ground in STOP and STANDBY modes, thereby reducing leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high-voltage MOS switch is used to maintain gate control voltage higher than well-bias voltage, then the switch can be completely opened to reduce leakage current, but the switch consumes a lot of power and occupies a large area
Solution Approach 1:
The patent changes the voltage parameter of the gate control signal dynamically based on operating mode. During STOP/STANDBY modes, the gate control voltage is raised to match or exceed the well-bias voltage to ensure complete switch opening and minimize leakage. During RUN mode, the gate control voltage is reduced to normal operating levels, significantly lowering power consumption. This dynamic parameter adjustment resolves the contradiction between reliable disconnection and power consumption.
2Use of energy by moving object
If a low-voltage MOS switch is used to keep gate control voltage equal to well-bias voltage, then power consumption and area are reduced, but the gate control voltage fails to track the well-bias voltage causing the switch to conduct leakage current
Solution Approach 1:
The patent implements dynamic gate control voltage adjustment based on the IC's operating mode. A mode detection circuit identifies whether the IC is in RUN, STANDBY, or STOP mode and accordingly adjusts the gate control voltage. During low-power modes, the gate voltage dynamically tracks the well-bias voltage to ensure complete switch opening. This dynamic behavior allows the use of low-voltage MOS switches while maintaining reliable leakage current reduction.
3Reliability
If the n-well region is biased with voltage higher than core supply voltage and p-well region with voltage lower than ground voltage during STOP and STANDBY modes, then the threshold voltage of CMOS transistor increases reducing leakage current, but the well-biasing circuit becomes more complex
Solution Approach 1:
The patent designs a multi-functional well-biasing circuit that performs multiple operations: it generates elevated n-well bias voltage and depressed p-well bias voltage during STOP/STANDBY modes to increase transistor threshold voltage and reduce leakage current. Simultaneously, it provides normal core supply voltage biasing during RUN mode. The circuit also includes mode detection and dynamic gate control voltage adjustment capabilities. This universal circuit design achieves leakage reduction while managing complexity through integrated multi-functionality.
Data Source
AI summary
A well-biasing circuit for an integrated circuit (IC) includes a well-bias regulator for providing well-bias voltages (n-well and p-well bias voltages) to well-bias contacts (n-well and p-well bias contacts) of each cell of the IC when the integrated circuit is in STOP and STANDBY modes. A switch is connected between a core power supply and the well-bias contact for connecting and disconnecting the core power supply and the well-bias contact when the IC is in RUN and STOP modes, and STANDBY mode, respectively. A voltage inverter circuit and a CMOS inverter circuit enable and disable the switch when the IC is in the RUN mode, and STOP and STANDBY modes, respectively.