Path-Based Well Connectivity Check for Plasma Damage Avoidance
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Solution Overview
Problem
Traditional verification tools fail to identify direct connectivity between victim and aggressor transistor wells due to intervening circuitry, leading to potential plasma-induced damage to thin gate dielectrics in integrated circuits.
Innovation Solution
A reliability verification tool that simulates a resistive network to determine connectivity between victim and aggressor transistor wells, considering shared intervening circuitry, to ensure proper manufacturing order and avoid plasma-induced damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional verification tools analyze layers step-by-step from substrate up, then the verification process is simple and systematic, but connectivity between victim and aggressor transistor wells is missed when intervening circuitry is present
Solution Approach 1:
The patent transitions from traditional 2D layer-by-layer verification to 3D path-based verification through the resistive network. The resistive network adds a new dimensional perspective that models electrical connectivity paths through intervening circuitry, enabling detection of connectivity relationships that are not apparent in standard 2D layout views.
Solution Approach 2:
The resistive network serves as an intermediary model between the layout design and the verification process. It abstracts the complex intervening circuitry into resistance values, allowing the verification tool to determine connectivity without directly analyzing every intermediate component, thus resolving the contradiction between accuracy and complexity.
2Adaptability or versatility
If victim and aggressor transistor wells are not directly connected but include intervening circuitry, then design flexibility is improved, but traditional verification tools fail to check connectivity rules
Solution Approach 1:
The patent replaces the mechanical/geometric connectivity checking approach with an electrical analog approach using resistive networks. Instead of checking for direct geometric connections between transistor wells, the system uses resistance values to model and verify electrical connectivity through intervening circuitry, maintaining reliability while accommodating design flexibility.
3Productivity
If gate dielectric is made thin to improve transistor performance, then device performance is improved, but plasma-induced damage risk increases during manufacturing
Solution Approach 1:
The system performs preliminary verification of connectivity rules before manufacturing by simulating the resistive network and detecting potential plasma-induced damage scenarios. This advance detection allows designers to modify layouts to prevent damage before fabrication occurs, enabling the use of thin gate dielectrics with improved performance while mitigating manufacturing risks.
Data Source
AI summary
This application discloses a computing system implementing a reliability verification tool to identify a portion of a layout design describing an integrated circuit includes a victim transistor having a gate connected to an aggressor transistor. The reliability verification tool can extract a resistance network for connections between the victim transistor and the aggressor transistor, and simulate the resistive network to determine connectivity between the wells of the victim transistor and the aggressor transistor occurs prior to the victim transistor having a gate connected to an aggressor transistor.