Semiconductor Well Contact Layout for Corrosion-Free Tap Cells
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Solution Overview
Problem
Semiconductor devices face challenges in maintaining high reliability and preventing defects or corrosion in well contacts due to complex and highly integrated structures, particularly when well taps of different conductivity types are shared with logic cells.
Innovation Solution
The semiconductor device incorporates a design with separate power rails and well taps, where well contacts do not overlap power rails, and includes additional contact vias to enhance voltage provision, reducing defects and corrosion by preventing sharing of well contacts as source/drain contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If well taps of different conductivity types are shared with logic cells to reduce device complexity, then device complexity is reduced, but reliability deteriorates due to defects and corrosion in well contacts
Solution Approach 1:
The patent divides the well contact structure into separate components: dedicated well contacts for tap cells and separate source/drain contacts for logic cells. This segmentation prevents the sharing of well contacts between tap cells and logic cells, eliminating the corrosion pathway while maintaining structural organization through distinct contact regions and associated wiring.
Solution Approach 2:
The patent extracts the well contact function from the shared structure and creates dedicated well contacts specifically for tap cells. By taking out the well contact function from the common structure used by both tap and logic cells, the patent eliminates the harmful interaction that causes corrosion while preserving the necessary electrical connections.
2Reliability
If additional contact vias are added to enhance voltage provision, then voltage provision is improved, but device complexity increases
Solution Approach 1:
The patent incorporates additional contact vias (well contact vias and connection wiring) during the preliminary design phase to establish multiple voltage provision pathways before operation. This preliminary action ensures that voltage can be reliably supplied through redundant routes, preventing future reliability issues without requiring complex runtime adjustments.
Solution Approach 2:
The patent introduces intermediate connection wiring and additional contact vias that act as mediators between the well taps and the power supply network. These intermediary elements provide alternative current paths that enhance voltage provision stability while maintaining a manageable structural complexity through organized routing.
Data Source
AI summary
According to some embodiments of the present disclosure, a semiconductor device includes a first power rail configured to provide a first voltage and extending in a first direction, a substrate comprising a first well having a first conductivity type and a second well having a second conductivity type, a first well tap having the first conductivity type, on the first well; a first source/drain region having the second conductivity type, on the first well; a first source/drain contact extending in a second direction and electrically connected to the first power rail, on the first source/drain region, a first connection wiring electrically connected to the first source/drain contact and extending in the first direction, and a first well contact electrically connected to the first connection wiring, on the first well tap.