IC Well-Diode Protection Circuit for Antenna Effect Damage
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Solution Overview
Problem
Miniaturization of integrated circuit (IC) devices has increased their susceptibility to damage due to factors like thinner gate dielectric thicknesses and lowered dielectric breakdown voltages, with the antenna effect being a significant cause of circuit damage, leading to yield and reliability concerns during semiconductor manufacturing.
Innovation Solution
Incorporating a pair of PID protection devices configured as a forward diode and a reverse diode electrically coupled in series between a doped well and a substrate to discharge electric charges accumulated during manufacturing, effectively mitigating well-PID issues and ensuring the IC devices can withstand working voltages without reliability issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If miniaturization is pursued to reduce power consumption and increase functionality, then device performance is improved, but susceptibility to damage from antenna effect increases
Solution Approach 1:
The patent introduces a PID protection circuit as an intermediary component between the antenna structure and the gate dielectric. This circuit includes a first diode connected between the antenna and ground, and a second diode connected between the antenna and a well region, which acts as a mediator to discharge accumulated electric charges before they can cause damage to the gate dielectric, thus resolving the contradiction between maintaining miniaturization benefits and preventing antenna effect damage.
Solution Approach 2:
The patent implements preliminary protective action by incorporating the PID protection circuit during the manufacturing process, specifically forming the protection devices before or during the antenna structure fabrication. This preliminary action ensures that charge discharge pathways are already in place before plasma processing steps that generate harmful charges, preventing damage before it occurs rather than addressing it after the fact.
2Length of moving object
If gate dielectric thickness is reduced to enable miniaturization, then device size is reduced, but dielectric breakdown voltage decreases making the device more vulnerable
Solution Approach 1:
The patent applies beforehand cushioning by providing a protective circuit structure that cushions or absorbs the impact of voltage spikes and charge accumulation before they can reach the thin gate dielectric. The diode-based protection circuit acts as a cushioning mechanism that diverts excess energy away from the vulnerable gate dielectric, enabling the use of thinner dielectrics without proportionally increasing breakdown risk.
3Reliability
If PID protection devices are added to mitigate antenna effect, then device reliability is improved, but chip area increases
Solution Approach 1:
The patent merges the PID protection function with existing device structures by integrating the protection circuit into the antenna support structure and well regions that are already part of the device architecture. The second diode is connected to a well region that serves both as a structural element and as part of the protection circuit, thereby combining multiple functions into a single integrated structure that provides protection without proportionally increasing chip area.
Solution Approach 2:
The patent implements multi-functionality by designing the well region to serve dual purposes: as a structural element of the device and as an integral part of the PID protection circuit. The well region acts as both a functional component of the semiconductor device and as a charge discharge pathway in the protection circuit, thereby providing universal functionality that reduces the need for separate dedicated protection structures and minimizes additional chip area requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution effectively mitigates plasma-induced gate oxide damage, ensuring reliable operation and yield by discharging accumulated electric charges, thus preventing undesirably high voltages across gate dielectrics and sustaining high working voltages without affecting chip area or functionality.
Implementation Method 1
Incorporating a pair of PID protection devices configured as a forward diode and a reverse diode electrically coupled in series between a doped well and a substrate to discharge electric charges accumulated during manufacturing
Data Source
AI summary
An integrated circuit (IC) device includes a substrate, first and second semiconductor devices correspondingly in different first and second doped regions in the substrate. A gate of the first semiconductor device is electrically coupled to a source/drain of the second semiconductor device. The IC device further includes a first protection device configured as one of a first forward diode and a first reverse diode, and a second protection device configured as the other of the first forward diode and the first reverse diode. The first forward diode and the first reverse diode are electrically coupled in series between the substrate and a doped well. The doped well is in the first doped region and a source/drain of the first semiconductor device is in the doped well. Alternatively, the doped well is in the second doped region, and the source/drain of the second semiconductor device is in the doped well.