Well-less TVS SCR for ESD Protection
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Solution Overview
Problem
Existing ESD protection devices in integrated circuits face challenges with high capacitance, which slows down signaling speeds, and inadequate holding voltage, making them unsuitable for high-speed applications and prone to latch-up, especially with smaller transistor sizes and lower power supply voltages.
Innovation Solution
The design eliminates the large N-well in the SCR structure, replacing it with a deep N+ region with high doping concentration, which reduces capacitance and increases holding voltage, achieving lower parasitic capacitance and higher hole recombination rates for improved thermal stability and robustness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large N-well is used in the SCR structure for ESD protection, then the holding voltage is sufficient and the device provides robust protection, but the capacitance increases which slows down signaling speeds
Solution Approach 1:
The patent removes the large N-well from the SCR structure, extracting the source of high capacitance while maintaining the essential P-N-P-N SCR functionality through alternative doping regions and geometry configurations that provide ESD protection with lower capacitance
Solution Approach 2:
The patent changes the doping parameters and geometric parameters of the SCR structure, using heavily doped P+ and N+ regions with optimized dimensions and spacing to achieve lower capacitance while maintaining sufficient holding voltage for reliable ESD protection
2Use of energy by moving object
If the transistor size is reduced to consume less power, then the power consumption decreases, but the device becomes more susceptible to over-voltage failure from ESD pulses
Solution Approach 1:
The patent applies different doping concentrations and structural characteristics to different regions of the device - heavily doped P+ and N+ regions provide high breakdown voltage and ESD robustness at critical locations, while the overall device geometry is scaled down to reduce power consumption in the core transistor
Solution Approach 2:
The patent creates a composite structure combining heavily doped P+ and N+ regions with optimized geometric configurations to achieve a device that simultaneously exhibits low-power characteristics and high ESD robustness, effectively combining contradictory properties in a single integrated structure
3Ease of manufacture
If standard CMOS processes are used for manufacturing, then the manufacturing cost is reduced and ease of manufacture is improved, but the ESD protection devices may not be robust enough against high-energy ESD pulses
Solution Approach 1:
The patent optimizes doping concentrations, region dimensions, and geometric parameters within standard CMOS process capabilities to achieve ESD robustness comparable to specialized processes, using parameter optimization rather than process complexity to enhance device performance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces capacitance, enhances holding voltage, and improves signaling speeds, making the ESD protection device more suitable for high-speed applications while preventing latch-up and thermal failure.
Implementation Method 1
replacing it with a deep N+ region with high doping concentration, which reduces capacitance and increases holding voltage, achieving lower parasitic capacitance and higher hole recombination rates for improved thermal stability and robustness
Implementation Method 2
Power clamp 326 is coupled between VDD and ground (VSS), and shunts current from an ESD pulse between the power rails
Implementation Method 3
ESD protection device 16 turns on and discharges a negative ESD pulse from I/O pad 10 to ground
Implementation Method 4
Transient Voltage Suppressor (TVS) device for electro-static-discharge (ESD) protection
Data Source
AI summary
A well-less Transient Voltage Suppressor (TVS) Silicon-Controlled Rectifier (SCR) has a P+ anode region that is not in an N-well. The P+ anode region 20 is surrounded by N+ isolation regions near the surface, and a deep N+ region underneath that is formed in a p-substrate. A N+ cathode region is formed in the p-substrate. The deep N+ region has a doping of 5×1018 to 5×1019/cm3, compared to a doping of 1×1016/cm3 for a typical N-well, or a doping of 1×1013 to 1×1015/cm3 for the p-substrate. The high doping in the deep N+ region causes a recombination current that can shunt half of the anode current. Since the deep N+ region is much shallower than an N-well, the sidewall capacitance is greatly reduced, allowing for higher speed applications.