Selective Well-Tie Extension for CMOS Latch-Up Prevention
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Solution Overview
Problem
Latch-up is a critical failure mechanism in IC design caused by parasitic bipolar junction transistors, leading to short-circuit conditions and potential damage to circuitry.
Innovation Solution
The implementation of selective well doping with deep lateral and deep P-type implants to act as collector guards or guard-rings for parasitic emitters, reducing the injected current that reaches latch-up trigger regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional design rules are followed to prevent latch-up by keeping parasitic devices apart, then latch-up immunity is improved, but device area increases and space efficiency decreases
Solution Approach 1:
The patent applies selective heavy doping (degenerate doping levels) to specific local regions (well-tie extension areas) rather than uniformly across the entire substrate. This creates localized high-recombination zones that prevent latch-up only where needed, maintaining low latch-up potential in other regions and allowing closer spacing of trigger regions without increasing overall device area
Solution Approach 2:
The patent changes the doping parameter (concentration) to degenerate levels in specific regions, fundamentally altering the electrical properties of those areas. This parameter change creates extremely high recombination rates that effectively eliminate latch-up risk in targeted zones, enabling more compact device layouts while maintaining reliability
2Reliability
If guard-rings are added to collect minority currents, then latch-up immunity is improved, but device complexity increases
Solution Approach 1:
The patent merges the well-tie function with the latch-up prevention function by extending the well-tie into the active region and applying heavy doping to it. This combined structure serves dual purposes: providing the well-tie connection and creating a high-recombination zone that prevents latch-up, thereby reducing device complexity compared to separate guard-ring structures
Solution Approach 2:
The heavily doped well-tie extension serves multiple functions simultaneously: it acts as a well-tie for biasing, creates a collector guard to collect minority currents, and forms a high-recombination zone to prevent latch-up. This multi-functionality reduces the need for separate protective structures, simplifying the overall device design
3Reliability
If supply taps are used to strap wells, then latch-up immunity is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent incorporates the heavy doping of the well-tie extension during the standard CMOS manufacturing process flow, performing the latch-up prevention action preliminarily during fabrication rather than requiring post-fabrication adjustments. This preliminary doping action is integrated into existing process steps, avoiding additional precision requirements
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances latch-up immunity by reducing the size of the 'hot zone' around parasitic emitters, allowing closer proximity of trigger regions without increasing latch-up potential, and providing improved space efficiency for IC design.
Implementation Method 1
The increased dopant level of the selected implants increases recombination rates which reduce the injected current that reaches the trigger regions where latch-up might otherwise be triggered
Implementation Method 2
latch-up solution uses selective implants for well ties with heavier doping than the guard-ring and has a deep implant profile
Data Source
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AI summary
A CMOS circuit including a substrate of a first conductivity type with an emitter of a second conductivity type formed on a surface of the substrate, a well tie of the first conductivity type formed between trigger regions and the emitter comprising a strip of heavier doping coupled to a supply-voltage reference, and a well-tie extension including a deep lateral implant of the first conductivity type that overlaps a portion of the well tie. The deep lateral implant may have a degenerate level of doping. The deep lateral implant may be extended to form a guard-ring surrounding the emitter. Also, a deep implant of the first conductivity type may be formed at a lower portion of a body of the substrate that overlaps at least a portion of a lower extent of the deep lateral implant. The well tie may be extended to form a deep-profile guard-ring surrounding the emitter.