Wet Etching Vertical Electrical Connections in 3D ICs
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Solution Overview
Problem
Current methods for forming through-silicon vias in 3D integrated circuits face challenges such as resputtering and difficulty in stopping the etching process without damaging metal pads, leading to potential short-circuits and inefficiencies in achieving precise electrical connections.
Innovation Solution
A method involving wet etching with a solution containing fluorhydric acid and glycerol is used to drill vias, followed by a pre-wetting and rinsing step, and a vacuum step to control the etching process, along with a copper diffusion barrier and seed layer formation for precise metallization, enabling the formation of vertical electrical connections with minimal damage and efficient copper deposition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If dry etching is used to drill vias through the insulating layer, then the via walls can be made straight, but resputtering occurs and metal pads may be damaged leading to short-circuits
Solution Approach 1:
The patent replaces dry etching (mechanical/physical process) with wet etching (chemical process) to eliminate resputtering. The wet etching solution chemically removes the insulating layer material without causing ion bombardment that leads to resputtering, thereby protecting metal pads while still achieving via formation.
Solution Approach 2:
The patent changes the etching mechanism from physical (dry etching) to chemical (wet etching), fundamentally altering the process parameters. This parameter change eliminates the harmful resputtering effect while maintaining via formation capability, and allows for better control over etching depth and selectivity.
2Manufacturing precision
If the etching process is stopped precisely to expose the device structure, then manufacturing precision is improved, but controlling the stopping point without damaging metal pads becomes difficult
Solution Approach 1:
The patent introduces a selective wet etching solution as an intermediary that etches the insulating layer at a controlled rate without attacking the metal pad. This intermediary chemical process allows precise stopping at the metal pad interface without causing damage, unlike dry etching where ion bombardment can erode the pad material.
Solution Approach 2:
The substitution of dry etching with wet etching provides better control over the etching process. The chemical etching mechanism allows for more predictable and controllable removal of insulating material, enabling precise exposure of the device structure without the harsh physical effects that can damage metal pads.
3Quantity of substance
If conventional metallization methods are used, then copper can be deposited in vias, but copper distribution may be non-uniform and diffusion into insulating layers may occur
Solution Approach 1:
The patent applies preliminary actions by first forming a liner layer and barrier layer in the via before copper deposition. The liner layer (e.g., silicon nitride or silicon oxynitride) is deposited to protect the via walls, and the barrier layer is applied to prevent copper diffusion into the insulating layer, ensuring uniform and controlled copper distribution.
Solution Approach 2:
The patent introduces intermediary layers (liner and barrier layers) between the via wall and the copper fill. These intermediary layers act as protective interfaces that control copper deposition, prevent diffusion, and ensure uniform distribution of copper within the via while protecting surrounding structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for precise and efficient formation of vertical electrical connections with reduced risk of resputtering and improved copper distribution, enhancing the reliability and performance of 3D integrated circuits by avoiding damage to conductive pads and ensuring uniform coating of insulating and copper layers.
Implementation Method 1
drilling of the insulating layer is at least partially performed by wet etching
Implementation Method 2
wet etching with a solution containing fluorhydric acid and glycerol
Implementation Method 3
a pre-wetting and rinsing step
Implementation Method 4
a vacuum step to control the etching process
Implementation Method 5
copper diffusion barrier and seed layer formation for precise metallization
Implementation Method 6
seed layer formation for precise metallization, enabling the formation of vertical electrical connections with minimal damage and efficient copper deposition
Data Source
AI summary
The invention proposes a method for forming a vertical electrical connection (50) in a layered semiconductor structure (1), comprising the following steps: —providing (100) a layered semiconductor structure (1), said layered semiconductor structure (1) comprising: —a support substrate (20) including an first surface (22) and a second surface (24), —an insulating layer (30) overlying the first surface (22) of the support substrate (20), and —at least one device structure (40) formed in the insulating layer (30); and —drilling (300) a via (50) from the second surface of the support substrate (20) up to the device structure (40), in order to expose the device structure (40); characterized in that drilling (300) of the insulating layer is at least performed by wet etching (320).