Wettable Flank Semiconductor Package for Lead Plating Isolation

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Solution Overview

Problem

Current semiconductor packages face challenges in efficiently electroplating leads and isolating die flags, leading to suboptimal solder wetting and package performance.

Innovation Solution

The semiconductor package design incorporates half-etched tie bars for electroplating lead ends and a trench to electrically isolate leads from die flags, with a mold compound encapsulating the structure to expose only the electroplated tie bar ends, enhancing solderability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional semiconductor packages are used with full encapsulation, then package protection and structural integrity are improved, but solder wetting and electroplating efficiency deteriorate

Engineering Contradiction:
Improvepackage protectionVSAvoidsolder wetting
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The patent applies local quality by creating a wettable flank region with different properties than the rest of the package. The sidewall is treated to be wettable to solder while other regions remain encapsulated and protected, allowing simultaneous achievement of protection and solderability through spatially differentiated properties.

Inventive Principle:
Principle #3Local quality

2Device complexity

If die flags are not electrically isolated from leads, then manufacturing simplicity is improved, but electrical interference and signal integrity deteriorate

Engineering Contradiction:
Improvemanufacturing simplicityVSAvoidsignal integrity
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The patent introduces a trench as an intermediary structure between the leads and die flags. This trench acts as a physical and electrical barrier that isolates the die flags from the leads, preventing electrical interference while maintaining a relatively simple manufacturing process that integrates with existing encapsulation steps.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Ease of manufacture

If tie bars are fully etched for electroplating, then electroplating coverage is improved, but structural strength and electrical connectivity deteriorate

Engineering Contradiction:
Improveelectroplating coverageVSAvoidtie bar integrity
Core Design Contradiction:
Ease of manufactureVSStrength

Solution Approach 1:

The patent applies partial action by performing a half-etch of the tie bars rather than complete etching. This partial etching exposes sufficient surface area for effective electroplating while retaining enough of the original tie bar structure to maintain structural strength and electrical connectivity, achieving the optimal balance between plating coverage and structural integrity.

Inventive Principle:
Principle #16Partial or excessive action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design improves the electroplating process, ensuring reliable solder wetting and package performance by exposing the electroplated tie bar ends and isolating die flags, resulting in improved electrical connectivity and reliability.

Implementation Method 1

Each end of the plurality of leads may include an electroplated end. The plurality of half-etched tie bars may be used to electroplate the plurality of leads.

Methodology Applied
Scientific EffectElectroplating: Electroplating

Data Source

PatentUS12176272B2Semiconductor package with wettable flank
Publication Date: 2024.12.24 SEMICON COMPONENTS IND LLC
  • US12176272B2 patent drawing
  • US12176272B2 patent drawing
  • US12176272B2 patent drawing

AI summary

Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.