Wettable Flank Lead Structure for Burr-Free QFN Soldering
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Solution Overview
Problem
Existing wettable flank-QFNs suffer from structural weaknesses due to burr defects caused by lead elongation during cutting operations, leading to short defects and hindering mass production.
Innovation Solution
The semiconductor device package incorporates barrier portions between leads, with tapered surfaces and gaps designed to accommodate solder elements, preventing burr formation and enhancing jointing strength, while allowing for increased lead pitch and distribution density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If cutting operations are performed to create wettable flanks, then soldering performance is improved, but burr defects occur due to lead elongation
Solution Approach 1:
The patent applies preliminary anti-action by designing a support structure (encapsulant with tapered space) that prevents the harmful effect of burr formation before it occurs. The tapered space provides structural support to the lead during cutting operations, counteracting the lead elongation that causes burrs, thereby maintaining both soldering performance and reliability
2Manufacturing precision
If wettable flanks are created to improve soldering quality, then visual inspection capability is improved, but short defects occur between leads
Solution Approach 1:
The patent uses an intermediary approach by introducing the encapsulant material as a mediating structure between the leads. The encapsulant with its tapered space provides physical separation and support, preventing the leads from coming into contact and forming short circuits, while still allowing the wettable flanks to function for soldering and inspection
3Manufacturing precision
If lead pitch is increased to reduce burr impact, then manufacturing tolerance is improved, but distribution density decreases
Solution Approach 1:
The patent applies parameter changes by modifying the geometric parameters of the encapsulant structure (tapered space angles, gap dimensions) to optimize the balance between lead pitch tolerance and distribution density. By adjusting these parameters, the design achieves both improved manufacturing tolerance and maintained lead density
Data Source
AI summary
A semiconductor device package is provided. The semiconductor device package includes a plurality of leads, an encapsulant, and a solder element. The plurality of leads includes a first lead. The encapsulant is disposed at two sides of the first lead. The solder element is disposed over a top surface of the first lead. In a cross-sectional view perspective, the first lead and the encapsulant collectively define a space tapering in a first direction from the top surface toward a lower surface of the first lead, and the space is configured to direct the solder element to flow from the top surface along a first lateral surface of the first lead toward a bottom portion of the space.