Wettable-Flank Semiconductor Package Pads for QFN Inspection
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Solution Overview
Problem
Existing semiconductor package formation methods do not effectively create wettable flanks, which are crucial for reliable electrical connections and inspection, especially in no-leads packages like quad-flat no-leads (QFN) and chip-on-lead (COL) packages.
Innovation Solution
The method involves forming semiconductor packages by coupling die to a pre-plated pad carrier with a metal carrier and pre-plated pads, wire bonding, applying a mold compound, and singulating, where each pad includes a solderable and wire bondable layer, with the wire bondable layer overhanging to form a mold lock and expose solderable layers on multiple sides, creating wettable flanks during the singulation process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a standard semiconductor package formation method is used, then the package can be manufactured efficiently, but wettable flanks are not formed, resulting in poor electrical connection reliability and inspection difficulty
Solution Approach 1:
The wire bondable layer is deposited to extend beyond the pad edges before die attachment, pre-forming the mold lock structure. This preliminary action ensures that wettable flanks will be created during subsequent singulation without requiring additional processing steps, thereby improving electrical connection reliability while maintaining manufacturing efficiency
Solution Approach 2:
The pad structure is segmented into distinct functional layers: a solderable layer for electrical connection, a wire bondable layer extending beyond the pad for mold lock formation, and an etch stop layer. This segmentation allows each layer to perform its specific function optimally, creating wettable flanks that enhance both connection reliability and inspection capability
2Reliability
If wettable flanks are formed by extending wire bondable layer, then electrical connection reliability and inspection capability are improved, but the device structure becomes more complex
Solution Approach 1:
The wire bondable layer serves multiple functions: it provides wire bonding surfaces during assembly and simultaneously forms the mold lock structure that creates wettable flanks during singulation. This multi-functionality reduces the need for separate structures, thereby improving reliability without proportionally increasing device complexity
Solution Approach 2:
The mold lock feature and wettable flank formation are merged into a single structural element created by the extended wire bondable layer. This consolidation eliminates the need for separate mold lock structures and wettable flank features, reducing overall device complexity while achieving both goals
3Area of stationary object
If no-leads package design is used, then footprint is reduced, but wettable flanks are not formed, resulting in inspection difficulty and connection reliability issues
Solution Approach 1:
The wettable flanks are created on the vertical sidewalls of the package through the extended wire bondable layer, utilizing the vertical dimension rather than requiring additional horizontal footprint. This allows no-leads packages to maintain their compact footprint while providing accessible wettable surfaces for inspection and connection
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures robust and reliable electrical connections and inspection by forming wettable flanks on the semiconductor packages, enhancing the reliability of the mold compound encapsulation and facilitating automatic optical inspection.
Implementation Method 1
The wire bondable layer may overhang the solderable layer and form a mold lock
Implementation Method 2
Each pad of the plurality of pads may include an etch stop layer directly coupled to the carrier, a solderable layer directly coupled to the etch stop layer, and a wire bondable layer directly coupled to the solderable layer
Data Source
AI summary
Implementations of methods of forming semiconductor packages may include coupling a plurality of die to a pad carrier that includes a carrier and a plurality of pads, wire bonding the plurality of die to the plurality of pads, applying a mold compound over the plurality of die, removing the carrier, and singulating a plurality of semiconductor packages.