Wettable Flank Semiconductor Package With Half-Etched Tie Bars
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Solution Overview
Problem
Existing semiconductor packages face challenges in efficiently encapsulating leads and tie bars while ensuring electrical isolation and promoting solder wetting.
Innovation Solution
The semiconductor package design includes a lead frame with half-etched tie bars, where the ends of the tie bars are exposed on the package's sidewalls, and the leads are electroplated to extend beyond the package surface, enhancing solder wetting.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the tie bars are fully etched to expose ends, then solder wetting is improved, but structural integrity and electrical isolation are compromised
Solution Approach 1:
Instead of fully etching the tie bars, the patent applies partial etching (half-etching) that exposes only the necessary lateral surfaces for solder wetting while leaving the top surfaces intact. This partial action provides sufficient solder access without compromising the structural integrity and electrical isolation that would be lost with full etching.
2Reliability
If more leads are exposed, then electrical connectivity is improved, but encapsulation complexity increases
Solution Approach 1:
The lead frame is designed with pre-positioned leads and tie bars in the mold compound before encapsulation. This preliminary arrangement allows the mold compound to be applied in a single operation, enclosing most components while leaving only the necessary lead ends exposed. This approach maintains electrical connectivity without requiring complex multi-step encapsulation processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design effectively encapsulates leads and tie bars, maintains electrical isolation, and improves solder wetting, leading to enhanced reliability and performance of semiconductor packages.
Implementation Method 1
An end of the first lead and an end of the second lead may each be electroplated
Implementation Method 2
The first lead and the second lead may each extend from the first sidewall at least eight micrometers (μm)... improving solder wetting
Data Source
AI summary
Implementations of the semiconductor package may include a first sidewall opposite a second sidewall, and a third sidewall opposite a fourth sidewall. Implementations of the semiconductor package may include a first lead and a second lead extending from the first sidewall and a first half-etched tie bar directly coupled to the first lead. An end of the first half-etched tie bar may be exposed on the third sidewall of the semiconductor package. Implementations of the semiconductor package may also include a second half-etched tie bar directly coupled to the second lead. An end of the second half-etched tie bar may be exposed on the fourth sidewall. An end of the first lead and an end of the second lead may each be electroplated. The first die flag and the second die flag may be electrically isolated from the first lead and the second lead.


