What-If Simulation System for Rapid HDL Design Verification
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Solution Overview
Problem
The chip design industry faces significant bottlenecks in verification due to the time-consuming nature of dynamic simulations, which require re-simulation and re-compilation for even minor design or signal changes, making it difficult to conduct multiple what-if changes efficiently.
Innovation Solution
A what-if simulation method and system that extracts a portion of the design based on a specified scope and time window, generates a test bench using simulation data, and feeds signal values to a simulator, allowing for rapid simulation of design changes without re-compiling the entire design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the whole design is re-simulated for each what-if change, then simulation accuracy is maintained, but simulation time and turnaround time increase significantly
Solution Approach 1:
The patent segments the design into hierarchical levels (full design, sub-designs, modules) and performs simulation at appropriate granularities. Instead of re-simulating the entire design for each what-if change, the system identifies and simulates only the affected sub-design or module, maintaining accuracy while reducing time consumption.
Solution Approach 2:
The system performs preliminary actions by pre-compiling the entire design and pre-simulating to generate baseline waveforms and data before what-if changes are applied. This preliminary simulation data is then reused and modified for subsequent what-if analyses, eliminating the need for full re-simulation and significantly reducing turnaround time.
2Stability of the object's composition
If the entire design is re-compiled for each what-if change, then design consistency is ensured, but compilation time increases
Solution Approach 1:
The system performs full compilation of the design in advance, before any what-if changes are processed. The compiled design is stored and reused for multiple what-if analyses, ensuring design consistency while avoiding repeated compilation overhead. Only when fundamental design changes occur is the compilation step repeated.
Solution Approach 2:
The compilation process is segmented into full design compilation and incremental updates. The system compiles the entire design once to establish a baseline, then applies what-if changes to the compiled representation without triggering full re-compilation, maintaining consistency through controlled update mechanisms.
3Reliability
If multiple what-if changes are conducted sequentially with full re-simulation, then each change is thoroughly verified, but the total turnaround time becomes troublesome
Solution Approach 1:
The system performs a preliminary full simulation to generate baseline data, waveforms, and timing information before conducting what-if changes. This preliminary action creates a reusable foundation that accelerates subsequent what-if analyses while maintaining verification thoroughness through targeted re-simulation of only affected areas.
Solution Approach 2:
Multiple what-if changes are handled by segmenting the simulation effort into a one-time full simulation phase followed by multiple rapid what-if analysis phases. Each what-if change leverages the preliminary simulation data and only re-simulates affected portions, enabling thorough verification of multiple scenarios without proportional increase in total turnaround time.
Data Source
AI summary
What-if simulation methods and systems are provided. A design coding in HDL (Hardware Description Language) and a simulation result corresponding to the design are provided. A what-if design scope and a what-if time window are received. A portion of the design is extracted from the design according to the what-if design scope, and primary input signals are determined during the extraction of the sub-design. Then, what-if simulation data is extracted from the simulation result according to the primary input signals and the what-if time window. A what-if test bench is generated according to the what-if simulation data, wherein the what-if simulation data is read, and the signal values are fed to a simulator according to the what-if test bench.