Wheatstone Bridge Impedance Sensing Circuit for High-SNR ADC Resolution
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Solution Overview
Problem
Existing analog to digital converters (ADCs) face challenges such as high power consumption, low resolution, and inadequate performance in various applications due to limited power budgets and resolution requirements.
Innovation Solution
The development of advanced ADC designs and architectures that provide high resolution digital format data by sensing analog current signals, featuring low power consumption, and capable of operating over a broad bandwidth from DC to over 10 MHz.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing ADC designs are used, then device simplicity is maintained, but power consumption is high and resolution is low
Solution Approach 1:
The ADC is divided into multiple parallel sub-ADCs (e.g., four 2-bit sub-ADCs) that process different segments of the input signal simultaneously. Each sub-ADC operates at lower resolution and power, but their combined output achieves high overall resolution through parallel processing and digital combination logic.
Solution Approach 2:
The design transitions from single-bit sequential processing to multi-bit parallel processing by adding spatial dimension (multiple parallel channels). This dimensional expansion allows simultaneous processing of multiple signal components, achieving higher effective resolution without proportionally increasing power consumption.
2Productivity
If existing ADC designs are used, then device complexity is low, but bandwidth is limited and performance is inadequate
Solution Approach 1:
The wide bandwidth input signal is segmented into multiple frequency or amplitude ranges, with each sub-ADC optimized for specific segments. This segmentation allows each simple sub-ADC to handle its portion efficiently while the aggregate system achieves wide overall bandwidth coverage.
Solution Approach 2:
The parallel sub-ADC architecture creates a universal ADC system that can handle multiple signal types, bandwidth requirements, and resolution demands simultaneously. The same basic sub-ADC units can be configured for different applications by adjusting the parallel combination logic.
3Measurement precision
If high resolution is achieved through traditional methods, then measurement precision improves, but power consumption increases
Solution Approach 1:
High resolution is achieved by segmenting the conversion process into multiple parallel low-resolution sub-converters. Each sub-ADC consumes minimal power, but their coordinated operation through digital logic combination produces high-resolution output equivalent to or exceeding traditional high-power ADCs.
Solution Approach 2:
Multiple low-resolution digital outputs from parallel sub-ADCs are merged through combinatorial logic circuits to produce a high-resolution composite output. This merging process achieves high effective resolution while each individual component operates at low power.
Data Source
AI summary
An impedance sensing circuit includes first and second current sources and first and second bias current sources that are appropriately coupled to first and second resistors. The impedance sensing circuit also includes a comparator that compares a first voltage based on the first terminal of the first resistor to a second voltage based on the first terminal of the second resistor to generate a comparator output signal. Either the comparator output signal or a digital signal based on the comparator output signal operates to regulate the current signals output from the first and second current sources so that the first voltage is same as the second voltage. The comparator output signal and the digital signal is representative of a difference between the first voltage and the second voltage that is based on an impedance difference between the first resistor and the second resistor.