Hardware-Accelerated Whirlpool Hash Authentication
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Solution Overview
Problem
Existing secure authentication systems using cipher-based hash functions face inefficiencies due to impractical, bulky, and power-intensive software implementations, leading to poor performance and limited energy efficiency, especially in high-performance and power-constrained devices.
Innovation Solution
A secure authentication system is implemented with hardware acceleration, optimizing the Whirlpool hash function using Galois Field arithmetic and fused scale/reduce circuits, with a microarchitecture that includes three sequential registers for add key computation, reducing sequential logic area and clock power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If software implementation of cipher-based hash function is used, then flexibility and adaptability are maintained, but performance is poor and energy consumption is high
Solution Approach 1:
The patent replaces software-based cryptographic hash computation with a dedicated hardware circuit implementation. The hardware circuit performs the cipher-based hash function computations directly in electronic logic, eliminating the overhead of software interpretation and execution. This substitution of software with specialized hardware achieves significant improvements in throughput and energy efficiency for secure authentication operations.
2Productivity
If hardware acceleration is implemented, then performance and throughput are improved, but device complexity increases
Solution Approach 1:
The hardware circuit is designed by segmenting the cryptographic hash function into distinct modular components including substitution boxes (S-boxes), permutation units, mixing functions, and round key generation modules. Each component is independently implemented and can be reused across multiple rounds of the hash function. This segmentation allows for systematic design, easier verification, and optimized resource utilization while maintaining high throughput performance.
3Speed
If extensive lookup tables are used for hash computation, then computation speed is improved, but area and energy penalties increase
Solution Approach 1:
The patent transforms the substitution operations from lookup table-based approaches to algebraic operations in Galois Fields. Instead of storing pre-computed substitution values in large lookup tables, the circuit performs field multiplication and inversion operations using optimized combinational logic. This parameter change from data-storage-based speedup to computation-based speedup dramatically reduces the circuit area while maintaining high computation speed through efficient algebraic operations.
4Reliability
If more sequential registers are used for add key computation, then computation accuracy is maintained, but clock power and area increase
Solution Approach 1:
The hardware circuit employs a pipelined architecture where add key operations are distributed across multiple clock cycles in a periodic manner. Instead of using numerous sequential registers that would require continuous clocking, the design uses a smaller number of registers updated periodically through the pipeline stages. This periodic action maintains computational accuracy while reducing the number of clocked elements, thereby lowering dynamic power consumption and clock tree complexity.
Data Source
AI summary
Various embodiments are generally directed to techniques for secure message authentication and digital signatures, such as with a cipher-based hash function, for instance. Some embodiments are particularly directed to a secure authentication system that implements various aspects of the cipher-based hash function in dedicated hardware or circuitry. In various embodiments, the secure authentication system may implement one or more elements of the Whirlpool hash function in dedicated hardware. For instance, the compute-intensive substitute byte and mix rows blocks of the block cipher in the Whirlpool hash function may be implemented in dedicated hardware or circuitry using a combination of Galois Field arithmetic and fused scale/reduce circuits. In some embodiments, the microarchitecture of the secure authentication system may be implemented with delayed add key to limit the memory requirement to three sequential registers.