Wide Atomic Sequences for Memory Operations
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Solution Overview
Problem
Current microprocessors are limited by fixed data word widths, restricting them to perform memory operations only up to twice their data word width, preventing support for wider memory operations such as 256-bit operations in 64-bit processors.
Innovation Solution
Implementing wide atomic sequences in hardware systems by augmenting load and conditional storing operations to allocate and check memory buffers, allowing for the execution of wide memory operations by storing data in concatenation of memory locations exceeding the standard data word width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If fixed data word width architecture is used, then processor simplicity is maintained, but memory operation width is limited to twice the data word width
Solution Approach 1:
The patent segments wide memory operations into multiple atomic operations that can be executed in sequence. For example, a 256-bit memory operation is divided into multiple 64-bit or 128-bit atomic operations, each operating within the processor's fixed data word width constraints. This allows the processor to achieve wider effective memory operations without changing its fundamental architecture.
Solution Approach 2:
The patent introduces an intermediary buffer structure that temporarily holds data during wide memory operations. This buffer acts as a mediator between the fixed-width processor and the wider memory operation requirements, allowing data to be accumulated and transferred in chunks that match the processor's native word width while achieving wider overall operations.
2Reliability
If atomic sequences are implemented to ensure uninterrupted execution, then memory space protection is improved, but operation overhead increases
Solution Approach 1:
The patent merges multiple atomic operations into a single logical wide operation by using memory buffers to combine intermediate results. Instead of treating each atomic operation separately, the buffer allows results from multiple atomic operations to be combined atomically, reducing the overall complexity of managing multiple atomic sequences while maintaining reliability.
Solution Approach 2:
The patent performs preliminary actions by allocating and preparing memory buffers before executing atomic sequences. This preliminary setup allows the atomic operations to proceed more smoothly by having pre-allocated storage for intermediate results, reducing the overhead of dynamic memory management during the critical atomic execution phase.
3Adaptability or versatility
If wide memory operations are supported beyond fixed data word width, then operational capability is improved, but hardware complexity increases
Solution Approach 1:
The patent adds another dimension to memory operations by introducing buffer-based intermediate storage. Instead of directly expanding the data path width, the solution uses a temporal dimension with buffers to accumulate and manage wide operations, effectively achieving wide memory access capability without proportionally increasing the spatial complexity of the memory access mechanism.
Data Source
AI summary
Implementations of wide atomic sequences are achieved by augmenting a load operation designed to initiate an atomic sequence and augmenting a conditional storing operation that typically terminates the atomic sequence. The augmented load operation is designed to further allocate a memory buffer besides initiating the atomic sequence. The conditional storing operation is augmented to check the allocated memory buffer for any data stored therein. If one or more data words are detected in the memory buffer, the conditional storing operation stores the detected data word(s) and another word provided as operand in a concatenation of memory locations. The achieved wide atomic sequences enable the hardware system to support wide memory operations and wide operations in general.