Wide-Bus Data Structure for IC Design
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Solution Overview
Problem
Current IC design tools lack efficient representations for wide-gates and wide-buses, leading to increased design time and suboptimal quality of results due to the inability to explicitly retain information about multi-input logical operations and multi-bit variables throughout the design flow.
Innovation Solution
The introduction of wide-gate and wide-bus data structures that explicitly represent multi-input logical operations and multi-bit variables, with bidirectional links to individual gate and wire data structures, allowing for improved performance and quality of results by maintaining this information throughout the IC design flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional IC design tools are used without wide-bus data structures, then the design flow can proceed with standard representations, but the design time increases and quality of results deteriorates due to loss of multi-bit variable information
Solution Approach 1:
The patent segments the IC design representation into two levels: wide-bus data structures that preserve multi-bit variable information at the conceptual level, and individual wire data structures that represent the physical implementation. This segmentation allows the system to maintain abstract wide-bus representations throughout the design flow while still supporting detailed wire-level analysis when needed, thereby preventing information loss without unnecessarily complicating every operation.
Solution Approach 2:
The patent introduces a new dimension of representation by adding wide-bus data structures that operate at a higher level of abstraction than traditional wire-based representations. This dimensional addition allows the system to simultaneously maintain both the abstract multi-bit variable information (wide-bus level) and the concrete wire-level details, enabling operations to be performed at the appropriate level without losing information across dimensional boundaries.
2Reliability
If wide-bus data structures with bidirectional links are introduced, then information about multi-bit variables is preserved throughout the design flow, but the device complexity increases
Solution Approach 1:
The patent extracts the essential wide-bus information (multi-bit variable representation) from the detailed wire-level representation and stores it separately in wide-bus data structures. This extraction allows the system to maintain a simplified wide-bus view for high-level operations while keeping wire-level details available when needed, reducing the complexity burden on any single data structure while preserving both levels of information.
Solution Approach 2:
The wide-bus data structures are designed to be multi-functional, serving both as containers for multi-bit variable information and as nodes in the bidirectional link system connecting to wire data structures. This universality allows a single data structure to fulfill multiple roles, reducing the need for separate specialized structures and thereby managing overall system complexity while maintaining reliability.
3Ease of operation
If wide-bus data structures are used to represent multi-bit variables, then operations can be performed on the wide-bus as a whole, but the implementation requires additional data structures and references
Solution Approach 1:
The patent introduces wide-bus data structures as intermediary objects that mediate between high-level design operations and low-level wire implementations. These intermediaries provide a simplified interface for wide-bus operations while automatically managing the complexity of underlying wire connections through bidirectional links, allowing operations to be performed on the wide-bus as a whole without manually managing individual wire complexity.
Data Source
AI summary
Systems and techniques are described for designing an integrated circuit (IC). Some embodiments explicitly represent wide-buses as distinct objects in an IC design data model. One or more IC design representations that are used in an IC design flow may natively support such wide-bus objects. These new objects can enable rapid access and preservation of wide-buses, thereby improving the runtime and/or quality of results (QoR) of an IC design system.