Wide Bus Pattern Matching Using Diagonal Detection
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Solution Overview
Problem
Field programmable gate arrays (FPGAs) used in network equipment test devices struggle to keep up with line rate data transmission and reception due to complex logic design and increased component requirements for detecting patterns across multiple clock cycles and packets on a data bus.
Innovation Solution
Implementing a wide bus pattern matching system that uses pattern compare blocks, diagonal detectors, and packet boundary detectors to identify matching patterns across multiple clock cycles and packets, allowing for efficient detection of patterns on a data bus by comparing n-bit portions of data and indicating matches within packet boundaries.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FPGAs are used in parallel to scan the data bus for patterns, then pattern detection capability is improved, but logic circuit complexity and component requirements increase
Solution Approach 1:
The data bus is divided into multiple segments, with each segment processed by a dedicated pattern compare block. This segmentation allows parallel processing of multiple pattern segments simultaneously, improving detection capability while keeping each individual compare block relatively simple in structure.
Solution Approach 2:
The patent introduces a diagonal arrangement of pattern compare blocks across multiple clock cycles, transforming the temporal dimension into a spatial-diagonal dimension. Patterns that span multiple clock cycles are detected by comparing them diagonally across time, eliminating the need for complex multi-cycle state machine logic.
2Productivity
If FPGAs are used in parallel to scan the data bus for patterns, then pattern detection capability is improved, but the number of required components increases
Solution Approach 1:
Each pattern compare block is designed as a universal unit that can compare any n-bit data segment against any n-bit pattern portion. This multi-functionality allows the same hardware block to be reused across different clock cycles and different pattern positions, reducing the total number of components needed compared to having dedicated comparators for each specific pattern position.
Solution Approach 2:
By arranging pattern compare blocks diagonally across clock cycles, the system reuses the same physical components for detecting patterns that span multiple cycles. A single compare block can participate in multiple pattern detection operations at different diagonal positions, effectively reducing component quantity while maintaining detection capability.
3Adaptability or versatility
If complex logic design is used to detect patterns spanning multiple clock cycles, then multi-cycle pattern detection is achieved, but logic circuit complexity increases
Solution Approach 1:
The patent transforms multi-cycle pattern detection from a temporal problem into a spatial-diagonal problem. Instead of using complex logic to track pattern state across cycles, the system arranges compare blocks diagonally so that each diagonal position naturally corresponds to a specific pattern alignment across time. This geometric transformation simplifies the logic required to detect patterns spanning multiple cycles.
Solution Approach 2:
The system pre-arranges pattern compare blocks in diagonal positions before data arrives, creating a ready-made template for detecting patterns of any length. This preliminary structural arrangement eliminates the need for dynamic logic control during operation, as the diagonal geometry itself encodes the multi-cycle detection logic.
Data Source
AI summary
A method for wide bus pattern matching includes, receiving, in a first clock cycle, a bus width of data from a data bus. The method further includes using pattern compare blocks to compare each n-bit portion of data from the data bus to a plurality of different n-bit pattern portions, n being an integer equal to a smallest boundary in which a pattern can start on the data bus. The method further includes detecting, using a plurality of diagonal detectors, matching pattern portions across the pattern compare blocks that are arranged in a diagonal. The method further includes detecting, using a packet boundary detector, when the matching pattern portions arranged in a diagonal indicate a matching pattern that falls within a set of packet boundaries. The method further includes indicating a positive match when the packet boundary detector indicates that the matching.