Wide Elastic Buffer for PCIe Clock Domain Synchronization
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Solution Overview
Problem
Existing PCIe devices face challenges in maintaining data integrity and synchronization due to frequency differences between transmitting and receiving devices, leading to potential overflow or underflow issues in elastic buffers.
Innovation Solution
A wide elastic buffer system is implemented, which includes a write controller, data buffer circuit, read controller, skip ordered set detector, and lane shifter. This system adjusts write and read pointers to compensate for frequency differences by adding or removing skip data elements, ensuring correct data ordering and synchronization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If independent clock generation circuits are used in PCIe devices, then device independence and flexibility are improved, but frequency differences between transmitting and receiving devices cause data synchronization issues and buffer overflow/underflow
Solution Approach 1:
An elastic buffer is introduced as an intermediary component between the transmitting and receiving clock domains. The buffer absorbs frequency differences by allowing data to be written at the transmitter's clock rate and read at the receiver's clock rate, preventing synchronization issues while maintaining device independence
Solution Approach 2:
The system dynamically adjusts the buffer's read and write pointers based on detected skip symbols. When frequency differences cause the buffer to approach overflow or underflow conditions, the pointer adjustment mechanism modifies the data flow rate to maintain synchronization
2Adaptability or versatility
If larger frequency tolerance is allowed (e.g., SRIS feature with 5000 ppm), then device compatibility is improved, but the risk of buffer overflow or underflow increases
Solution Approach 1:
The elastic buffer employs dynamic pointer adjustment mechanisms that adapt to varying frequency differences. The read and write pointers are continuously modified based on skip symbol detection, allowing the system to handle large frequency tolerances like SRIS's 5000 ppm while maintaining buffer stability
Solution Approach 2:
The system uses skip symbols as feedback signals to detect and correct frequency mismatches. When the buffer level approaches critical thresholds, the feedback mechanism triggers pointer adjustments to restore balance, enabling reliable operation even with large frequency variations
3Reliability
If skip symbols are inserted periodically to prevent overflow or underflow, then buffer stability is improved, but data transfer efficiency decreases due to additional processing
Solution Approach 1:
The system uses skip symbols to rapidly adjust buffer levels when frequency mismatches occur. By inserting or removing data elements at critical moments, the skip mechanism rushes through the correction process quickly, minimizing the impact on overall data transfer efficiency while maintaining buffer stability
Data Source
AI summary
A receiving device uses an elastic buffer that is wider than the number of data elements transferred in each cycle. To compensate for frequency differences between the transmitter and the receiver, the transmitting device periodically sends a skip request with a default number of skip data elements. If the elastic buffer is filling, the receiving device ignores one or more of the skip data elements. If the elastic buffer is emptying, the receiving device adds one or more skip data elements to the skip request. To maintain the ordering of data despite the manipulation of the skip data elements, two rows of the wide elastic buffer are read at a time. This allows construction of a one-row result from any combination of the data elements of the two rows. The column pointers are adjusted appropriately, to ensure that they continue to point to the next data to be read.