Wide-Gap Semiconductor Device Polysilicon Well Region Potential Control
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Solution Overview
Problem
Wide gap semiconductor devices experience abnormal potential increases and current concentration issues due to displacement current and parasitic bipolar operations, particularly in regions below the gate pad, which existing configurations struggle to address effectively.
Innovation Solution
A wide gap semiconductor device design featuring a polysilicon layer in contact with a well region, electrically connected to a source pad, and optionally including a field insulating film, which can be in Schottky or ohmic contact, to prevent potential increases and current concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a well region of second conductivity type is provided below a gate pad, then the device structure is formed, but abnormal potential increase occurs due to displacement current during switching operations
Solution Approach 1:
A polysilicon layer is introduced as an intermediary between the well region and the gate pad. This polysilicon layer acts as a mediator that prevents the abnormal potential increase from propagating through the well region during switching operations, thereby stabilizing the potential while maintaining the necessary device structure.
Solution Approach 2:
The polysilicon layer changes the electrical parameters of the well region interface by providing a controlled conductivity path. This parameter change prevents the abnormal potential increase caused by displacement current, as the polysilicon layer modifies the electrical characteristics at the critical interface region.
2Reliability
If an n-type region is added in a p-type well region below a gate pad, then potential increase is addressed, but breakdown occurs due to current concentration from parasitic bipolar operations
Solution Approach 1:
The polysilicon layer serves as an intermediary that distributes the current flow evenly across the well region interface. This prevents current concentration that would otherwise occur at specific points, thereby avoiding breakdown from parasitic bipolar operations while still controlling the potential.
3Reliability
If a Schottky electrode formed of metallic material is used below a gate pad, then potential control is achieved, but manufacturing complexity and cost increase considerably
Solution Approach 1:
The polysilicon layer replaces the expensive and complex metallic Schottky electrode with a simpler, more cost-effective material that can be easily deposited using standard semiconductor manufacturing processes. This achieves the same potential control function without the manufacturing complexity and high costs associated with metallic Schottky electrodes.
Solution Approach 2:
The invention changes the material parameter from metallic Schottky electrode to polysilicon layer, which has different electrical and physical properties. This parameter change maintains the potential control function while dramatically simplifying the manufacturing process and reducing costs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The polysilicon layer's lower sheet resistance and simplified manufacturing process effectively prevent potential increases in the well region, reducing manufacturing costs and complexity while maintaining device performance.
Implementation Method 1
the polysilicon layer and the well region are in Schottky contact
Implementation Method 2
the polysilicon layer and the well region are in ohmic contact
Data Source
AI summary
A wide gap semiconductor device has: a drift layer 12 using a first conductivity type wide gap semiconductor material; a well region 20, being a second conductivity type and provided in the drift layer 12; a polysilicon layer 150 provided on the well region 20; an interlayer insulating film 65 provided on the polysilicon layer 150; a gate pad 120 provided on the interlayer insulating film 65; and a source pad 110 electrically connected to the polysilicon layer 150.