Wide Gate Cut Dielectric Stack for Level Fill and Short Prevention
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Solution Overview
Problem
The challenge in integrated circuit fabrication lies in forming both narrow and wide gate cuts with highly disparate critical dimensions, as current techniques fail to adequately fill wider gate cuts, leading to issues like sagging and pooling of conductive material, which can cause shorts.
Innovation Solution
A multi-layer dielectric structure is formed using a first dielectric layer via atomic layer deposition, a second layer with a different material composition via chemical vapor deposition, and a third layer with higher density via flowable CVD, ensuring complete filling and a level top surface to prevent metal pooling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If current filling techniques are used for wide gate cuts, then narrow gate cuts can be filled, but wide gate cuts are not adequately filled leading to sagging and pooling of conductive material
Solution Approach 1:
The gate cut filling process is segmented into multiple deposition stages: first depositing dielectric material to form a base layer, then forming a mandrel structure, and finally depositing additional dielectric material to complete the fill. This segmentation allows each stage to be optimized independently, ensuring complete filling without sagging or pooling.
Solution Approach 2:
A mandrel structure is formed preliminarily within the gate cut before the final dielectric material deposition. This preliminary structure serves as a support framework that prevents sagging and pooling during subsequent material deposition, ensuring complete and uniform filling of the gate cut region.
2Reliability
If gate cuts are made wider to improve device isolation, then isolation effectiveness increases, but filling becomes inadequate leading to conductive material pooling
Solution Approach 1:
The filling process for wide gate cuts is divided into segments: initial dielectric deposition, mandrel formation, and final dielectric fill. This segmentation enables wide gate cuts to be completely filled by providing structural support at intermediate stages, preventing the pooling issue that would otherwise occur in wide regions.
Solution Approach 2:
A mandrel structure acts as an intermediary element formed within the wide gate cut during the filling process. This intermediary structure provides mechanical support to prevent sagging and pooling of conductive material, enabling reliable filling of wide gate cuts while maintaining device isolation effectiveness.
3Ease of manufacture
If single-layer dielectric structures are used in gate cuts, then manufacturing is simpler, but the structure cannot prevent metal pooling in wide gate cuts
Solution Approach 1:
The gate cut structure uses composite dielectric materials arranged in multiple layers: a first dielectric material deposited initially, a mandrel structure formed from dielectric material, and a second dielectric material completing the fill. This composite structure provides the mechanical support needed to prevent metal pooling while maintaining manufacturing feasibility through standardized deposition processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the successful formation of both narrow and wide gate cuts with a substantially level top surface, preventing metal pooling and ensuring reliable integrated circuit performance.
Implementation Method 1
a first dielectric layer via atomic layer deposition
Implementation Method 2
a second layer with a different material composition via chemical vapor deposition
Implementation Method 3
a third layer with higher density via flowable CVD
Data Source
AI summary
Techniques are provided herein to form semiconductor devices that include one or more wide gate cuts having a multi-layer dielectric structure. A semiconductor device includes a gate structure around or otherwise on a semiconductor region. The gate structure may be interrupted, by any number of gate cuts that extend through an entire thickness of the gate structure and which include dielectric material. Some of the gate cuts may be at least 2× wider than others. Such wide gate cuts may include a first dielectric layer with a first material composition, a second dielectric layer on the first dielectric layer with a second material composition elementally different from the first material composition, a third dielectric layer on the second dielectric layer with a greater density than the second dielectric layer, and a dielectric fill within a remaining volume of the wide gate cut and on the third dielectric layer.