Wide-Input Comparator Circuit With Reduced NMOS-PMOS Output Delay
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Solution Overview
Problem
Current wide-input common mode voltage comparators experience delays between NMOS and PMOS comparators due to their circuit types, leading to reduced accuracy and increased skew in integrated circuits.
Innovation Solution
A wide-input common mode voltage comparator design that includes a first comparator for high common mode voltages and a second comparator for low common mode voltages, both with threshold voltages between −100 to 100 mV, and a summing circuit to create a single-ended output, utilizing native NMOS transistors with reduced threshold voltage to minimize delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If NMOS and PMOS comparators are used to accommodate high and low common mode voltages respectively, then the wide input common mode voltage range is achieved, but delay occurs between the outputs of the comparators
Solution Approach 1:
The patent changes the threshold voltage parameter of the input transistors to be between -100 to 100 mV, which is significantly lower than conventional transistors. This parameter change allows both NMOS and PMOS comparators to operate with reduced threshold voltage, thereby reducing the delay between their outputs while maintaining the ability to accommodate wide input common mode voltage ranges from -0.5V to 3.0V
Solution Approach 2:
The patent applies different transistor threshold voltage characteristics to different parts of the comparator circuit. Specifically, the input transistors are designed with reduced threshold voltage (-100 to 100 mV) to minimize delay, while other transistors in the circuit maintain conventional characteristics. This local differentiation optimizes the critical path without compromising overall circuit functionality
2Ease of manufacture
If conventional transistors with higher threshold voltage are used, then the circuit is easier to manufacture with standard processes, but the delay between comparators increases and accuracy decreases
Solution Approach 1:
The patent modifies the threshold voltage parameter of input transistors to range between -100 to 100 mV, which reduces the delay between NMOS and PMOS comparator outputs. This parameter change improves measurement precision and timing accuracy while remaining compatible with standard CMOS fabrication processes, thus maintaining ease of manufacture
Solution Approach 2:
The patent introduces dynamic threshold voltage control through the use of native NMOS transistors whose threshold voltage can be adjusted through biasing conditions. This allows the circuit to optimize its timing characteristics in real-time while maintaining compatibility with standard manufacturing processes
Data Source
AI summary
A design for a wide input common mode voltage comparator is provided which reduces the delay between outputs from component comparators. The wide input common mode voltage comparator includes a first comparator configured to receive a differential input. The first comparator is further configured to accommodate high common mode voltages. The wide input common mode voltage comparator further includes a second comparator configured to receive the differential input. The first comparator is further configured to accommodate low common mode voltages. Additionally, the threshold voltages of the active devices within the comparator are between −100 to 100 mV. Furthermore, the wide input common mode voltage comparator includes a summing circuit configured to receive the outputs of the first and second comparators to create a single-ended output.