Wide-Input Receiver Circuit for Low-Power DRAM Voltage Mismatch
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The independent variation between DRAM signaling voltage and receiver power supply voltage in mobile devices poses challenges for low power operation, leading to inefficient current discharge and voltage stress on transistors, particularly in receivers with wide input voltage ranges.
Innovation Solution
A low power receiver design that employs a pass transistor controlled by a control circuit to manage input signal passage during low and high voltage modes, using a source follower transistor to reduce threshold voltage during high voltage modes and prevent stress on thin-oxide inverter devices, allowing for high-speed operation without voltage stress.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the receiver uses a standard inverter design to receive data from DRAM, then it can operate with standard signaling voltages, but it consumes excessive power and generates unnecessary current discharge when there is a voltage mismatch between DRAM signaling voltage and receiver power supply voltage
Solution Approach 1:
The patent applies dynamics by making the receiver circuit configuration adaptive and changeable based on voltage conditions. The circuit dynamically switches between different operational modes (pass transistor on/off states) depending on the relationship between input signal voltage and power supply voltage, allowing the receiver to optimize its power consumption while maintaining compatibility with varying DRAM signaling voltages
Solution Approach 2:
The patent changes the operational parameters of the receiver circuit based on voltage conditions. By monitoring the voltage relationship between the input signal and power supply, the circuit adjusts its operating state (blocking vs. passing mode) to match the input voltage range, thereby reducing power consumption while maintaining adaptability to different voltage levels
2Adaptability or versatility
If the receiver is designed to tolerate high input voltages, then it can accept signals from high voltage mode DRAM, but it loses input amplification capability needed for low voltage swings in low voltage mode
Solution Approach 1:
The receiver employs dynamic switching between two distinct circuit configurations: one optimized for high voltage tolerance (pass transistor blocking mode) and another optimized for low voltage amplification (pass transistor passing mode). This dynamic reconfiguration allows the circuit to adapt its characteristics based on the operating voltage level, achieving both high voltage tolerance and low voltage amplification capability at different times
Solution Approach 2:
The receiver circuit is segmented into multiple functional paths: a pass transistor for high voltage mode operation and a source follower transistor for low voltage mode operation. Each segment is optimized for specific voltage ranges, with the pass transistor providing high voltage tolerance when blocking and the source follower providing amplification when active, allowing the circuit to handle both high and low voltage scenarios effectively
3Speed
If the inverter is constructed from thin-oxide devices to facilitate high-speed operation, then it achieves high-speed performance, but it becomes vulnerable to voltage stress from high voltage input signals
Solution Approach 1:
The pass transistor serves as an intermediary protective element between the high voltage input signal and the thin-oxide inverter. When the input voltage exceeds safe levels, the pass transistor blocks the signal path, preventing direct voltage stress on the vulnerable thin-oxide devices. This intermediary mechanism allows the use of fast thin-oxide inverters while protecting them from high voltage damage through active voltage-level monitoring and conditional signal blocking
Data Source
Figure 1
Figure 2
Figure 3
AI summary
An input receiver is provided with a pass transistor that is controlled to pass an input signal to an inverter only while a first binary state for the input signal equals a low voltage. The input receiver also includes a source follower transistor configured to pass a threshold-voltage-reduced version of the input signal while the first binary state of the input signal equals a high voltage greater than the low voltage.