Wide-IO NAND Data Staging for LPDDR Timing Compliance

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Solution Overview

Problem

Existing memory systems struggle to meet low-latency and high-throughput demands for AI workloads due to increased data movement bandwidth and storage capacity requirements, leading to challenges in data center performance.

Innovation Solution

Implement memory bus timing synchronization techniques for wide-IO NAND memory, including data staging methods that estimate cycle times, store host commands, and manage latency through data staging commands, allowing the system to mask latency and meet DDR timing constraints without modifying existing LPDDR controllers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If data staging commands are implemented to mask latency, then timing constraints are met, but device complexity increases

Engineering Contradiction:

Improvetiming constraint complianceVSAvoidcontroller complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements data staging commands that pre-fetch data from NAND memory into a buffer before the host actually needs it. The controller estimates cycle times for host commands and initiates data staging operations in advance, masking the inherent latency of NAND memory. This preliminary action allows the system to meet DDR timing constraints without requiring fundamental changes to the controller architecture.

Inventive Principle:

Principle #10Preliminary action

2Productivity

If wide-IO NAND memory is used to increase storage capacity, then data movement bandwidth is improved, but latency increases

Engineering Contradiction:

Improvedata movement bandwidthVSAvoidmemory access latency

Core Design Contradiction:

ProductivityVSLoss of time

Solution Approach 1:

The system performs data staging operations in advance by issuing host commands to the NAND memory controller that initiate data retrieval before it is actually needed. The controller estimates cycle times and schedules data staging commands accordingly, so that data is ready in the buffer when the host requires it, effectively masking the latency of wide-IO NAND memory while maintaining high data movement bandwidth.

Inventive Principle:

Principle #10Preliminary action

3Adaptability or versatility

If existing LPDDR controllers are modified to support wide-IO NAND, then adaptability is improved, but ease of manufacture decreases

Engineering Contradiction:

Improvememory system compatibilityVSAvoidcontroller modification complexity

Core Design Contradiction:

Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent implements a software-based data staging layer that copies the functionality of DDR memory timing management without requiring hardware modifications to existing LPDDR controllers. By implementing the data staging command processing in the existing controller firmware or software, the system achieves wide-IO NAND compatibility while maintaining the original controller hardware design, thus preserving ease of manufacture.

Inventive Principle:

Principle #26Copying

Data Source

PatentUS20260037131A1Systems and methods of data staging for dram timing compliance in NAND memory

Publication Date: 2026.02.05 SAMSUNG ELECTRONICS CO LTD

AI summary

Provided are systems, methods, and apparatuses for memory bus timing synchronization. In one or more examples, the systems, devices, and methods include data staging for memory module, the method comprising: storing one or more parameters of a host command in a command table based on receiving, from a host, a host command for the memory of the memory module; estimating a cycle time for completing the host command at the memory; and providing, to the host via the memory of the memory module, data in a buffer of the memory module, the data being stored in the buffer based on the memory completing the host command.