Wide M1 Pin Standard Cell Routing Efficiency
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Solution Overview
Problem
Existing standard cell architectures in integrated circuit design are limited by insufficient via enclosure, leading to reduced routing efficiency and increased chip size due to limited pin access points, and prior solutions that enhance via enclosure result in increased design rule check errors and implementation difficulties.
Innovation Solution
A standard cell design with a first metal layer pin having a width greater than the via width to satisfy enclosure rules, allowing the pin to extend vertically past the via, thereby increasing the number of pin access points and improving routing efficiency while reducing chip size and design rule check errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the M1 pin width is increased to satisfy via enclosure rules, then via enclosure is improved, but the number of available pin access points decreases
Solution Approach 1:
The patent transitions from a conventional square M1 pin to a rectangular M1 pin with increased width in one dimension. This dimensional change allows the pin to provide sufficient lateral enclosure for the via while extending vertically to maintain multiple access points, thereby resolving the contradiction between via enclosure and pin accessibility
Solution Approach 2:
The M1 pin is designed with non-uniform dimensions - wider in the lateral direction to provide via enclosure and extended in the vertical direction to maintain access points. This localized quality differentiation allows the same pin structure to simultaneously satisfy both via enclosure requirements and pin accessibility requirements
2Adaptability or versatility
If the M1 pin extends vertically past the via, then pin access points are increased, but via enclosure may be compromised
Solution Approach 1:
The M1 pin implements different dimensional characteristics in different directions: increased width in the lateral direction ensures sufficient via enclosure, while vertical extension provides additional access points. This localized quality approach allows simultaneous satisfaction of both via enclosure and pin accessibility
Solution Approach 2:
The patent uses a rectangular pin geometry that exploits different spatial dimensions - lateral width for via enclosure and vertical height for access point multiplication. This dimensional differentiation resolves the contradiction by addressing each requirement in its appropriate dimension
3Reliability
If conventional pin designs are used, then design rule check errors are reduced, but routing efficiency decreases and chip size increases
Solution Approach 1:
The patent changes the geometric parameters of the M1 pin from conventional dimensions to optimized dimensions - specifically increasing the width and adjusting the vertical height. This parameter optimization enables the pin to satisfy design rules while providing better routing efficiency and reduced chip size
Data Source
AI summary
Embodiments described herein provide approaches for improved circuit routing using a wide-edge pin. Specifically, provided is an integrated circuit (IC) device comprising a standard cell having a first metal layer (M1) pin coupled to a second metal layer (M2) wire at a via. The M1 pin has a width greater than a width of the via sufficient to satisfy an enclosure rule for the via, while the M1 pin extends vertically past the via a distance substantially equal to or greater than zero. This layout increases the number of available pin access points within the standard cell and thus improves routing efficiency and chip size.